JPH0427730B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal generation circuit such as a control signal supplied from a microcomputer to various control devices, and more particularly to a signal generation circuit in which the number of pulses of the signal can be set.

As a signal generating circuit for a conventional single-chip microcomputer, for example, there is one using a timer counter with a reload function. This signal generation circuit uses a down counter as a timer counter, and the timer counter is initialized by a microprocessor (hereinafter referred to as CPU). Then, the clock signal supplied to the timer counter is counted down, and when it reaches zero, the flip-flop is inverted. According to this configuration, the flip-flop is inverted in its state with a synchronization equal to the product of the clock signal synchronization and the initial value of the timer counter. That is, the flip-flop outputs a signal with a predetermined period.

However, in a signal generating circuit using a timer counter with a reload function as described above, it is not possible to easily set the number of pulses of the output signal. In other words, in order to specify the number of pulses in a conventional signal generation circuit, the CPU must
It is necessary to load the set value into the timer counter a predetermined number of times. However, this approach has the disadvantage that the CPU is unable to perform other arithmetic processing during this time, and the burden on the software increases.

Therefore, the present invention provides a register that stores the set value of the timer counter and a number counter that counts the output of the timer counter. After the output of the timer counter reaches a predetermined number, for example, the set value of the register is By not loading the counter, the number of pulse signals corresponding to the set value of the number counter is automatically output, and by changing the set value of the number counter, the number of pulses of the output signal can be easily output. The purpose is to solve the above problems by making it possible to change the

The present invention will be explained below based on the drawings.

FIG. 1 shows an embodiment of a signal generating circuit according to the present invention.

In the figure, 1 is a CPU, 2 is a decoder, 3 is a reload register, and 4 is a number counter.

Decoder 2 is connected to the CPU via address bus 5a.
1, and the reload register 3 and number counter 4 are connected to the CPU via the data bus 5b.
Connected to 1.

Then, the decoder 2 decodes the signal output from the CPU 1 to the address bus 5a, and
1 to the reload register 3, and load the setting value from the number counter 4 and flip-flop 6.
are set and reset respectively.

The reload register 3 takes in and stores the set value of a timer counter 7, which will be described later, from the CPU 1 via the data bus 5b in response to the set signal P _S1 outputted from the decoder 2.

The number counter 4 consists of a down counter, and a set value indicating twice the desired number of pulses is entered from the CPU 1 via the data bus 5b in response to the set signal P _S2 outputted from the decoder 2.
is set. The number counter 4 counts down the pulse signal output from the timer counter 7, and when its content becomes zero, the output _Qc is set to a high level and the flip-flop 6 is set. The flip-flop 6 is reset by the signal _PS2 output from the decoder 2.

The timer counter 7 consists of a down counter,
The clock signal CLK is counted down from a predetermined set value, and when the count reaches zero, a pulse signal is generated.
Print Q _t . Then, the output is set to high level by ANDing the output signal _Qt of the timer counter 7 and the output _Q1 of the flip-flop 6.
An AND gate 8 is provided, and the output of this AND gate 8 is supplied together with the signal P _S2 to a transfer gate 10 via an OR gate 9. This transfer gate 10 is composed of, for example, an n-channel MOSFET, and when the gate electrode is set to a high level, the gate is opened and the set value A stored in the reload register 3 is taken into the timer counter 7, and the timer counter 7 is set to the set value A.

Reference numeral 11 denotes a trigger flip-flop which is inverted by the output Q _t of the timer counter 7, and the output Q ₂ of this flip-flop 11 is supplied as a control signal to various control devices.

Next, the operation of the above signal generation circuit will be explained.

A signal output from the CPU 1 to the address bus 5a is decoded by the decoder 2, and first a set signal P _S1 is output. Then, this set signal P _S1 is supplied to the reload register 3, and the CPU 1
From there, the timer counter setting value A is loaded into the reload register 3 and stored. Subsequently, when the set signal P _S2 is output from the decoder 2, the set value B is taken into the number counter 4 from the CPU 1, and the number counter 4 is set to the set value B.
Flip-flop 6 is reset and output _Q1 becomes
As shown in FIG. 2, the level is set to high.

Further, when the set signal P _S2 is output from the decoder 2, the transfer gate 10 is opened via the OR gate 9, and the set value A stored in the reload register 3 is transferred to the timer counter 7.
The timer counter 7 is set to the set value A.

Then, the timer counter 7 receives the clock signal.
Each time CLK comes in, 1 is subtracted from the set value A. Then, when the content of the timer counter 7 becomes zero, a pulse signal _Qt is output. The flip-flop 11 is inverted by this signal _Qt , and the output _Q2 of the flip-flop 11 is changed from low level to high level.

In addition, the pulse output signal Q _t of the timer counter 7
is supplied to the number counter 4, and the number counter 4
goes to count down the signal Q _t . moreover,
The output signal Q _t of the timer counter 7 is supplied to one input terminal of the AND gate 8 . However,
The other input terminal of the AND gate 8 has already been brought to a high level by the output _Q1 of the flip-flop circuit 6. Therefore, when the signal Q _t comes in, the output of AND gate 8 is set to high level,
Transfer gate 10 is opened via OR gate 9. As a result, the set value A stored in the reload register 3 is loaded into the timer counter 7, and the timer counter 7 is set to the set value A again. Then, the timer counter 7 counts down the clock signal CLK again, and when it reaches zero, the pulse signal _Qt is output. As a result, the output _Q2 of the flip-flop 11 is changed from high level to low level, and the number counter 4 is changed from high level to low level.
1 is subtracted from the current value of , and the timer counter 7 is set to the set value A.

By repeating the above operations, the current value of the number counter 4 is decremented, and when it reaches zero, the pulse signal Q _c is output.

For example, if the set value A of the timer counter 7 is set to 10 and the set value B of the number counter 4 is set to 8, a pulse signal Q _t is output every time the timer counter 7 or clock counts 10, and the signal Q When eight _t 's are output, the contents of the number counter 4 become zero and the signal Q _c is output. By this time, the flip-flop 11 has output a signal of four pulses.
Q ₂ is being output.

When the signal Q _c is output from the number counter 4,
Flip-flop 6 is set. the result,
The output _Q1 of flip-flop 6 is changed to low level, and AND gate 8 and OR gate 9
Transfer gate 10 is closed via.
Thereafter, the set value A stored in the register 3 will no longer be taken into the timer counter 7. Therefore,
The pulse signal _Qt is no longer output from the timer counter 7, and the output _Q2 of the flip-flop 11 remains at a low level.

In other words, in this circuit, the flip-flop 11 outputs a signal Q ₂ with a pulse count that is half the set value B of the number counter 4.

In this way, the signal with a set number of pulses
When Q ₂ is used as a control signal for, for example, a clock alarm, a telephone bell, or a step motor, it can be used to specify the number of times the alarm or bell rings,
It becomes possible to precisely control the rotation angle of the motor.

As explained above, in the signal generation circuit according to the present invention, once appropriate setting values are entered from the CPU into the reload register and the number of times counter, a signal with the desired period and number of pulses is automatically output. It becomes like this. Furthermore, by changing the set values, the period and number of pulses of the signal can be easily changed. This allows the CPU
When generating a control signal of a predetermined number of pulses from the signal generation circuit based on an interrupt request, etc.,
Once the set values are entered into the reload register and the number of times counter, you can immediately return to the original program and perform other arithmetic processing. Therefore, the CPU utilization rate is improved and the burden on the software is reduced.

Note that in the circuit of the embodiment described above, it is also possible to change the duty ratio of the output signal by sequentially changing the set value taken into the reload register by the CPU.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal generating circuit according to the present invention, and FIG. 2 is a timing chart thereof. 1...CPU, 3...Reload register, 4...Number of times counter, 7...Timer counter, 6, 11...Flip-flop, A, B...Setting value, CLK...Clock signal.

Claims (1)

[Claims] 1. A timer counter that counts clock signals;
A register that stores the set value of the timer counter, a switch that connects the register and the timer counter, a number counter that stores the desired set value based on a control signal, and inputs the output pulse from the timer counter. a first flip-flop circuit, a second flip-flop circuit provided between the number counter and the switch, and a logic gate whose inputs are the output of the second flip-flop circuit and the output pulse from the timer counter. , the timer counter is set to the set value stored in the register via the switch, and when the set value is counted, it outputs a pulse signal, and the second flip-flop circuit is reset by the control signal and output. is brought to a high level,
Each time the pulse signal is output, the switch is turned on via the logic gate and the set value stored in the register is set in the timer counter, and the number counter is controlled by the output pulse of the timer counter. and when the desired set value is counted, an output signal is generated and the second flip-flop circuit is set so that the output of the second flip-flop circuit is set to a low level, and
The output is configured such that a signal of a predetermined number of pulses is output from the first flip-flop circuit only until the switch is turned off via the logic gate and the desired set value is counted. A signal generation circuit featuring: 2. A microprocessor, a timer counter that counts clock signals, a register that stores the set value of the timer counter, a switch that connects the register and the timer counter, and a switch that calculates the desired set value based on the control signal. a first flip-flop circuit that receives the output pulse from the timer counter; a second flip-flop circuit provided between the number counter and the switch; and an output of the second flip-flop circuit and the timer counter. and a signal generation circuit having a logic gate which inputs the output pulse from the counter, and the timer counter is configured to generate a signal every time a set value stored in the register is set via the switch and the set value is counted. outputs a pulse signal to the second flip-flop circuit, and the second flip-flop circuit is reset by the control signal to make the output high level;
Each time the pulse signal is output, the switch is turned on via the logic gate and the set value stored in the register is set in the timer counter, and the number counter is controlled by the output pulse of the timer counter. and when the desired set value is counted, an output signal is generated and the second flip-flop circuit is set so that the output of the second flip-flop circuit is set to a low level, and
The output is transmitted through the logic gate to turn off the switch, and a signal of a predetermined number of pulses is output from the first flip-flop circuit as a control signal for the control device only until the desired set value is counted. A microcomputer characterized in that it is configured to: