JPH04175937A - Microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the need to rewrite the set values of reload registers to be supplied to a timer every time the counted value of the timer reaches a specific value to enter an overflow state and to make time intervals of the output of an overflow signal different by providing the single timer and plural reload registers. CONSTITUTION:The microcomputer is equipped with the single timer 6 and reload registers 5A and 5B. When the set values of the reload registers 5A and 5B are supplied to the timer 6, the timer 6 counts the supplied counted values and outputs the overflow signal Sv when reaching the set values to send the set values of the different reload registers 5A and 5B to the timer. The timer 6 begins to count the set values supplied from the different reload registers every time the overflow signal Sv is outputted. Consequently, every time the timer 6 outputs the overflow signal Sv, the time intervals of the output of the overflow signal Sv by the timer 6 are made different without varying the set values of the reload registers 5A and 5B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer incorporating a timer and a reload register.

[Conventional technology]

FIG. 2 is a block diagram of a conventional microcomputer with a built-in timer and reload register. A count source C3 is applied to the timer 6 via a count source input line 1, and a set value of a reload register 5 is applied via a reload line 2. The output signal S0, which is the overflow signal of the timer 6, is output to the output signal line 3, and the interrupt request signal SA is output to the interrupt signal line 4.

Next, the operation of this microcomputer will be explained. Timer 6 counts the count source C8 given from count source input line 1, and when the count value of timer 6 reaches the set value given to it and overflows, the output signal line 3
At the same time, the interrupt request signal SA on the interrupt request signal line 4 is set to the "H" level.

At the same time, the set value of the reload register 5 is given to the timer 6.

[Problem to be solved by the invention]

The conventional microcomputer timer described above outputs an overflow signal at predetermined time intervals according to a set value given from a reload register.

Therefore, when changing the time interval for outputting the overflow signal, it is necessary to apply the next set value to the reload register after the timer count reaches a predetermined value and overflows. Alternatively, it is necessary to use multiple timers with different set values. However, since there is a limit to the number of timers built into a microcomputer, there is a problem in that the number of different setting values that can be provided is limited.

In view of this problem, the present invention eliminates the need to rewrite the set value of the reload register given to the timer each time the count value of the timer reaches a predetermined value and overflows, and the time interval at which the overflow signal is output can be made different. The purpose is to provide microcomputers.

[Means to solve the problem]

A microcomputer according to the present invention includes a single timer and a plurality of reload registers.

[Effect]

Give the reload register setting value to the timer.

The timer counts the given set value and outputs an overflow signal when the set value is reached. When an overflow signal is output, a different reload register setting value is given to the timer. Thereby, each time the timer outputs an overflow signal, it starts counting the set value given from a different reload register.

Therefore, each time the timer outputs an overflow signal, the time interval at which the timer outputs the overflow signal can be varied without changing the set value of the reload register.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram of a microcomputer according to the present invention. A count source Cs is applied to the timer 6 via the count source input line 1, and an overflow signal Sv outputted from the timer 6 when the count value of the timer 6 reaches a set value is applied to the flip-flop 7. The flip-flop 7 outputs an output signal S0 to the output signal line 3,
An interrupt request signal SA is output to the interrupt request signal line 4.

The count source C3 and the overflow signal S0
are respectively three-person AND circuits (hereinafter referred to as AND circuits) 8
, 9 are input to the input terminals. The output signal S0 of the flip-flop 7 is connected to the input terminal of the AND circuit 8 and the AND circuit 9.
is input to the low active input terminal of The reload register 5A reload signal SL is a 3-state buffer (
A load signal S from the reload register 5B is sent to the timer 6 via the NO and reload lines 2, hereinafter referred to as buffers.

is applied to the timer 6 via the buffer 11 and the reload line 2. The output of the AND circuit 8 is applied to the buffer 10, and the output of the AND circuit 9 is applied to the buffer 11.

Next, the operation of the microcomputer configured as described above will be explained.

Now, for example, a set value larger than the set value of the reload register 5B is set in the reload register 58, and a load signal S with the set value of the reload register 5A is first given to the timer 6 via the buffer 10 and the reload line 2. , the flip-flop 7 is set. The timer 6 counts the count source C8, and when the count value reaches the set value, the timer 6 outputs the "H" level overflow signal Sv, which is applied to the flip-flop 7, and the output signal S0 of the flip-flop 7 becomes " It is held at "L" level. As a result, the "L" level output signal S0 is input to the input terminal of the AND circuit 8, the logic is not established, and the buffer 10 is turned off. - On the other hand, the low active input 2 terminal of the AND circuit 9 receives the "L" level output signal S.
0 is input, the logic is established, and the output of the AND circuit 9 turns the buffer 11 on. Then, a load signal SL with the set value of the reload register 5B is applied to the timer 6 via the buffer 11 and the reload line 2. When the count value reaches the newly given set value, the timer 6 inputs an "H" level overflow signal Sv to the flip-flop 7, and its output is inverted and held at the "H" level. As a result, the "H" level output signal S0 is input to the low active input terminal of the AND circuit 9, and the logic is not established.
The logic holds true. Then, the output of the AND circuit 8 is applied to the buffer 10 to turn the buffer 10 on, and the set value to the reload register 5 is applied to the timer 6.

In this way, each time the timer 6 outputs the overflow signal Sv, the set value to the reload register 5 and the set value to the reload register 5B are alternately given to the timer 6. When the timer 6 counts the set value given from the reload register theory, it takes a long time until the overflow signal Sv is output, and when the timer 6 counts the set value given from the reload register 5B, the overflow signal The time until Sv is output is shortened, and the time the overflow signal Sv is at "H" level and the time it is at "L" level are different. Thereby, flip-flop 7
The duty of the pulses of the output signal S0 and the interrupt request signal SA output by the controller can be set as appropriate.

Furthermore, the duty of the output signal S0 or the time interval for outputting the interrupt request signal Sa can be varied without rewriting the set values of the reload registers 5A and 5B.

In addition, if you change the setting value of reload register 5A or 5B or the setting value of reload register 5A and 5B,
The duty of the output signal S0 can be changed, and the time interval for outputting the interrupt request signal SA can be changed. In this case, it is desirable to stop the operation of the timer 6 and rewrite the set values of the reload registers 5A and 5B.

In this embodiment, the setting value of the load 4 register 5A is set larger than the setting value of the reload register 5B, but this is merely an example. Further, the number of reload registers is not limited to two.

〔Effect of the invention〕

As described in detail above, the present invention uses a single timer and a plurality of reload registers to appropriately set the duty of the output signal without changing the set value of the reload register. Therefore, it is possible to provide a microcomputer that can improve the efficiency of using the timer of the microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer according to the present invention, and FIG. 2 is a block diagram of a conventional microcomputer. 5A, 5B... Reload register 6... Timer 7... Flip-flop 8.9... AND circuit 10.11... 3-state buffer Note that in the figures, the same reference numerals are the same or equivalent parts. shows. Agent Masuo Oiwa S^ Figure 2

Claims (1)

[Claims] (1) In a microcomputer configured to change the setting value of a timer that counts the setting value given from the reload register, it is equipped with a single timer and multiple reload registers, and the count value of the timer is changed accordingly. A microcomputer characterized in that the timer outputs an overflow signal when a given set value is reached, and each time the timer outputs an overflow signal, the set values of each reload register are sequentially given to the timer.