JPS6257442U - - Google Patents

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Publication number
JPS6257442U
JPS6257442U JP14857585U JP14857585U JPS6257442U JP S6257442 U JPS6257442 U JP S6257442U JP 14857585 U JP14857585 U JP 14857585U JP 14857585 U JP14857585 U JP 14857585U JP S6257442 U JPS6257442 U JP S6257442U
Authority
JP
Japan
Prior art keywords
parallel data
terminal
shift register
output
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14857585U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14857585U priority Critical patent/JPS6257442U/ja
Publication of JPS6257442U publication Critical patent/JPS6257442U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案のパラレル入力シリアル出力
回路の一実施例を示すブロツク図、第2図はこの
考案のパラレル入力シリアル出力回路の応用例を
示すブロツク図である。 1…タイミング制御部、2,22…シフトレジ
スタ、2a〜2n,22a〜22n…パラレルデ
ータ入力端子、4…出力端子、5…出力合成器。
FIG. 1 is a block diagram showing an embodiment of the parallel input serial output circuit of this invention, and FIG. 2 is a block diagram showing an application example of the parallel input serial output circuit of this invention. DESCRIPTION OF SYMBOLS 1... Timing control part, 2, 22... Shift register, 2a-2n, 22a-22n... Parallel data input terminal, 4... Output terminal, 5... Output combiner.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パラレルデータを入力するパラレルデータ入力
端子を有しその一番端子が接続されたシフトレジ
スタと、上記シフトレジスタにロード信号を与え
て上記一番端子に与えられたパラレルデータをデ
ータ無し信号として出力し、かつ出力データの必
要なタイミング時にシフトパルスを上記シフトレ
ジスタに与えて上記パラレルデータ入力端子に入
力されたパラレルデータからシリアルデータを出
力させるタイミング制御部とを具備するパラレル
入力シリアル出力回路。
A shift register having a parallel data input terminal to which parallel data is input is connected to the first terminal thereof, and a load signal is given to the shift register to output the parallel data given to the first terminal as a no-data signal. and a timing control unit that applies a shift pulse to the shift register at a timing when output data is required to output serial data from the parallel data input to the parallel data input terminal.
JP14857585U 1985-09-28 1985-09-28 Pending JPS6257442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14857585U JPS6257442U (en) 1985-09-28 1985-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14857585U JPS6257442U (en) 1985-09-28 1985-09-28

Publications (1)

Publication Number Publication Date
JPS6257442U true JPS6257442U (en) 1987-04-09

Family

ID=31062976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14857585U Pending JPS6257442U (en) 1985-09-28 1985-09-28

Country Status (1)

Country Link
JP (1) JPS6257442U (en)

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