JPS60166052U

JPS60166052U - Port expansion circuit

Info

Publication number: JPS60166052U
Application number: JP5222284U
Authority: JP
Inventors: 西村　勝歳; 高崎　正彦
Original assignee: 株式会社　フジソク
Priority date: 1984-04-10
Filing date: 1984-04-10
Publication date: 1985-11-05

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はこの考案に係わるポート拡張回路の一実施例を
示す回路構成図、第２図は第１図の動作を説明する、た
めに示す波形図である。１１・・・ＣＰＵ、　ＴＤＯＰ・・・時分割出力ポート
、ＩＰ・・・スイッチ入力ポート、ＳＴＢ・・・ストロ
ーブ出カポ−）、ＤＯＰ・・・データ出力ポート、１５
□〜１５４．１７□〜１７３・・・アンド回路、１６１
〜１６４・・・ラッチ回路。FIG. 1 is a circuit configuration diagram showing an embodiment of a port expansion circuit according to this invention, and FIG. 2 is a waveform diagram shown to explain the operation of FIG. 1. 11...CPU, TDOP...Time division output port, IP...Switch input port, STB...Strobe output capo), DOP...Data output port, 15
□~154.17□~173...AND circuit, 161
~164...Latch circuit.

Claims

[Scope of utility model registration request]

(1) A control means that outputs a strobe signal and a time division control signal by executing a data output command or a transfer command, and a plurality of storage means capable of storing data output from the control means; A port expansion circuit comprising means for selecting the storage means based on the strobe signal and the time division control signal and storing output data corresponding to the strobe signal.

(2) The port expansion circuit according to claim 1, wherein the control means is provided with a logic circuit that allows external input signals to be selectively input based on the time-sharing control signal.