JPS63537U - - Google Patents

Info

Publication number
JPS63537U
JPS63537U JP1986093736U JP9373686U JPS63537U JP S63537 U JPS63537 U JP S63537U JP 1986093736 U JP1986093736 U JP 1986093736U JP 9373686 U JP9373686 U JP 9373686U JP S63537 U JPS63537 U JP S63537U
Authority
JP
Japan
Prior art keywords
serial data
clock signal
period
signal
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986093736U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986093736U priority Critical patent/JPS63537U/ja
Publication of JPS63537U publication Critical patent/JPS63537U/ja
Pending legal-status Critical Current

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  • Maintenance And Management Of Digital Transmission (AREA)
  • Digital Computer Display Output (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第3図、第5図は本考案の実施例を示
す回路図、第2図、第4図、第6図は、その波形
図である。 3,10,11……シフトレジスタ、6,12
……リトリガラブルモノマルチ、5,16,17
……表示手段。
FIGS. 1, 3, and 5 are circuit diagrams showing an embodiment of the present invention, and FIGS. 2, 4, and 6 are waveform diagrams thereof. 3, 10, 11...shift register, 6, 12
...Retriggerable Mono Multi, 5, 16, 17
...Display means.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シリアルデータ信号とこのシリアルデータ信号
と同期したクロツク信号を入力してシリアルデー
タを表示するシリアルデータ表示装置において、
前記シリアルデータ信号及びクロツク信号を入力
するシフトレジスタと、クロツク信号を入力とし
て、その準安定期間が前記クロツク信号の周期よ
りも長く、シリアル転送の繰り返し周期よりも短
く設定されたリトリガラマブルモノマルチと、前
記シフトレジスタに接続された表示手段を備える
ことを特徴とするシリアルデータ表示装置。
In a serial data display device that displays serial data by inputting a serial data signal and a clock signal synchronized with the serial data signal,
A shift register to which the serial data signal and the clock signal are input; and a retriggerable monochrome device which receives the clock signal and whose metastable period is set to be longer than the period of the clock signal and shorter than the repetition period of the serial transfer. 1. A serial data display device comprising: a multiplier; and display means connected to the shift register.
JP1986093736U 1986-06-19 1986-06-19 Pending JPS63537U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986093736U JPS63537U (en) 1986-06-19 1986-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986093736U JPS63537U (en) 1986-06-19 1986-06-19

Publications (1)

Publication Number Publication Date
JPS63537U true JPS63537U (en) 1988-01-05

Family

ID=30956563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986093736U Pending JPS63537U (en) 1986-06-19 1986-06-19

Country Status (1)

Country Link
JP (1) JPS63537U (en)

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