JPH033055U - - Google Patents

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Publication number
JPH033055U
JPH033055U JP6192489U JP6192489U JPH033055U JP H033055 U JPH033055 U JP H033055U JP 6192489 U JP6192489 U JP 6192489U JP 6192489 U JP6192489 U JP 6192489U JP H033055 U JPH033055 U JP H033055U
Authority
JP
Japan
Prior art keywords
circuit
timing
data
phase inversion
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6192489U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6192489U priority Critical patent/JPH033055U/ja
Publication of JPH033055U publication Critical patent/JPH033055U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図はこの考案に係るデータの保
持回路の実施例を示し、第1図は第1の実施例の
ブロツク図、第2図及び第3図は第1の実施例の
タイムチヤート、第4図は第2の実施例のブロツ
ク図、第5図及び第6図は第2の実施例のタイム
チヤートである。 主な符号の説明、6……EXNOR回路、7,
10,12……Dタイプフリツプフロツプ回路、
9……マイクロコンピユータ、11……位相反転
回路、C……クロツク、D……データ。
1 to 6 show embodiments of the data holding circuit according to this invention, FIG. 1 is a block diagram of the first embodiment, and FIGS. 2 and 3 are timing diagrams of the first embodiment. FIG. 4 is a block diagram of the second embodiment, and FIGS. 5 and 6 are time charts of the second embodiment. Explanation of main symbols, 6...EXNOR circuit, 7,
10, 12...D type flip-flop circuit,
9...Microcomputer, 11...Phase inversion circuit, C...Clock, D...Data.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ保持のタイミングを指示するタイミング
指示回路と、このタイミング指示回路に基づきク
ロツクの位相を反転させることのできる位相反転
回路と、この位相反転回路の出力であるクロツク
でデータを保持するDタイプフリツプフロツプ回
路とで構成したことを特徴とするデータの保持回
路。
A timing instruction circuit that instructs the timing of data retention, a phase inversion circuit that can invert the phase of the clock based on this timing instruction circuit, and a D-type flip-flop that holds data using the clock that is the output of this phase inversion circuit. 1. A data holding circuit comprising a loop circuit.
JP6192489U 1989-05-30 1989-05-30 Pending JPH033055U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6192489U JPH033055U (en) 1989-05-30 1989-05-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6192489U JPH033055U (en) 1989-05-30 1989-05-30

Publications (1)

Publication Number Publication Date
JPH033055U true JPH033055U (en) 1991-01-14

Family

ID=31590612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6192489U Pending JPH033055U (en) 1989-05-30 1989-05-30

Country Status (1)

Country Link
JP (1) JPH033055U (en)

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