JPH01111341U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart of Fig. 1, Fig. 3 is a diagram showing a conventional serial data input/output device, and Fig. 4 is a timing chart of Fig. 3. It's a chat. In the figure, 1 is an output side device, 2 is a computer, 3 is a register, 4 is a P/S converter, 5 is a counter, and 6
1 is an input side device, 7 is an S/P converter, 8 is a timing controller, 9 is a computer, 10 is a clock generator, 11 is a star bit detection circuit, and 12 is a clock generator. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] A computer that outputs data in parallel, a register that latches and outputs the output of the above computer, a parallel-to-serial converter that inputs the output of the above register, converts it to serial data, and a counter that counts the number of bits in the above-mentioned parallel-to-serial converter. a serial-to-parallel converter that inputs the output of the parallel-to-serial converter of the above-mentioned output-side device, converts it to parallel data, and inputs the data from the above-mentioned serial-to-parallel converter; , a computer that outputs a data update signal to a register that constitutes the output side device, a frequency setting signal and a transfer start signal from the computer that input the frequency setting signal and a transfer start signal, and a counter and parallel that constitute the serial-to-parallel converter and the output side device. 1. A serial data input/output device comprising an input side device constituted by a timing controller that outputs a transfer clock to the serial converter and outputs a transfer end signal to the computer.