JPH0486950U - - Google Patents

Description

[Brief explanation of drawings]

Figure 1 is a functional block diagram of the pulse output package, Figure 2 is a block diagram of the pulse conversion circuit, and Figure 3 is a block diagram of the pulse conversion circuit.
Figure 4 shows the block diagram of the data selector, Figure 4 shows the time chart when creating a pulse train for time measurement, Figure 5 shows the IC logic diagram of the binary counter, and Figure 6 shows the timing diagram at the time of pulse input. It's a chat. FIG. 1, 1...Data buffer, 2...Pulse width output circuit, 3...Pulse train output circuit, 4...
Pulse conversion circuit, 5...Data selector, 6...
...binary counter. FIG. 2, 1...Address decoder, 2...Flip-flop, 3...Data buffer, 4...
...Data selector, 5...AND circuit. FIG. 3, 1...address decoder, 2...data buffer, 3...data buffer, 4...
...binary counter.

Claims (1)

[Scope of utility model registration request] A data buffer that inputs and outputs data between the CPU and pulse output package, a status buffer that outputs status to the CPU, a control circuit that controls the package, and a pulse that converts data from the CPU into pulse width. In a pulse output package consisting of a width output circuit and a pulse train output circuit that converts data from the CPU into a pulse train, there is a pulse converter circuit that converts the pulse width data into time measurement pulses (pulse train) by ANDing the pulse width data with the pulse output basic clock. , an input waveform shaping circuit that converts the time measurement pulses converted by the pulse conversion circuit and pulse train data output by the pulse train output circuit into 8-bit parallel data that can be read by the CPU, and a ripple binary counter. A pulse output diagnostic circuit comprising a bit binary counter and a data switching device that sends either a time measurement pulse obtained by converting pulse width data or pulse train data to an 8-bit binary counter.