JPH02112045U - - Google Patents
Info
- Publication number
- JPH02112045U JPH02112045U JP2108689U JP2108689U JPH02112045U JP H02112045 U JPH02112045 U JP H02112045U JP 2108689 U JP2108689 U JP 2108689U JP 2108689 U JP2108689 U JP 2108689U JP H02112045 U JPH02112045 U JP H02112045U
- Authority
- JP
- Japan
- Prior art keywords
- data
- transmission device
- communication section
- data transmission
- serial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Time-Division Multiplex Systems (AREA)
- Communication Control (AREA)
Description
第１図はこの考案のデータ伝送装置のシステム
構成の一実施例を示すブロツク図、第２図は第１
図の実施例の作用状態を示すフローチヤート図、
第３図は第１図で示した実施例のクロツク信号波
形図、第４図乃至第６図は各々従来例を示すブロ
ツク図送信データの波形図、クロツク信号波形図
である。
Ａ，Ｂ……装置、ａ，ｂ……通信装置（通信部
）、Ａ′，Ｂ′……シリアルデータ、Ｄ，〜Ｄ４
……パラレルデータ、(A)，(B)……データバス、
ＨＳ１，ＨＳ２……ハンドシエイク信号、Ｔ……
待ち時間、１，２……タイミング作成回路。
FIG. 1 is a block diagram showing an embodiment of the system configuration of the data transmission device of this invention, and FIG.
A flowchart diagram showing the working state of the embodiment shown in the figure,
FIG. 3 is a clock signal waveform diagram of the embodiment shown in FIG. 1, and FIGS. 4 to 6 are block diagrams showing transmission data waveforms and clock signal waveform diagrams, respectively, showing conventional examples. A, B...device, a, b...communication device (communication section), A', B'...serial data, D, ~D4
...parallel data, (A), (B) ...data bus,
HS1, HS2...handshake signal, T...
Waiting time, 1, 2... timing creation circuit.
Claims (1)
２本のデータ線で通信するＰ／Ｓ，Ｓ／Ｐ変換器
からなる通信部を備えたデータ伝送装置であつて
、 上記通信部にデータバス上のステツプ２調歩同
期してシリアル通信を可能にするタイミング作成
回路を設けたことを特徴とするデータ伝送装置。[Scope of Claim for Utility Model Registration] A data transmission device equipped with a communication section consisting of a P/S and S/P converter that converts multiple data buses into serial data and communicates via two round-trip data lines. . A data transmission device, characterized in that the communication section is provided with a timing generation circuit that enables serial communication in step 2 start-stop synchronization on the data bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108689U JPH02112045U (en) | 1989-02-23 | 1989-02-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108689U JPH02112045U (en) | 1989-02-23 | 1989-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02112045U true JPH02112045U (en) | 1990-09-07 |
Family
ID=31238009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2108689U Pending JPH02112045U (en) | 1989-02-23 | 1989-02-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02112045U (en) |
-
1989
- 1989-02-23 JP JP2108689U patent/JPH02112045U/ja active Pending
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