JPS63171846U - - Google Patents

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Publication number
JPS63171846U
JPS63171846U JP6564787U JP6564787U JPS63171846U JP S63171846 U JPS63171846 U JP S63171846U JP 6564787 U JP6564787 U JP 6564787U JP 6564787 U JP6564787 U JP 6564787U JP S63171846 U JPS63171846 U JP S63171846U
Authority
JP
Japan
Prior art keywords
interface
signals
device adapter
centronics
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6564787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6564787U priority Critical patent/JPS63171846U/ja
Publication of JPS63171846U publication Critical patent/JPS63171846U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は第1図に示す実施例における書き込み動
作を説明するためのタイムチヤートである。 1……CPU、2……フアームウエア、3……
ロジツク回路、31……書込制御回路、32……
読出制御回路、41,51……レシーバ回路、4
2,52……ドライバ回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart for explaining the write operation in the embodiment shown in FIG. 1...CPU, 2...firmware, 3...
Logic circuit, 31...Write control circuit, 32...
Read control circuit, 41, 51...Receiver circuit, 4
2,52...Driver circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セントロニクスインタフエースの信号をデバイ
スアダプタインタフエース(以下、DAI)に変
換するためのロジツク回路と、前記ロジツク回路
の制御を行なうフアーム・ウエアと、前記セント
ロニクスインタフエースおよび前記デバイスアダ
プタインタフエースからの信号を受信するための
一対のレシーバ回路と、前記セントロニクスイン
タフエースおよび前記デバイスアダプタインター
フエースへ信号を送信するための一対のドライバ
とを含むことを特徴とする変換アダプタ。
A logic circuit for converting signals from the Centronics interface into a device adapter interface (hereinafter referred to as DAI), firmware for controlling the logic circuit, and converting signals from the Centronics interface and the device adapter interface. A conversion adapter comprising a pair of receiver circuits for receiving signals and a pair of drivers for transmitting signals to the Centronics interface and the device adapter interface.
JP6564787U 1987-04-28 1987-04-28 Pending JPS63171846U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6564787U JPS63171846U (en) 1987-04-28 1987-04-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6564787U JPS63171846U (en) 1987-04-28 1987-04-28

Publications (1)

Publication Number Publication Date
JPS63171846U true JPS63171846U (en) 1988-11-08

Family

ID=30902916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6564787U Pending JPS63171846U (en) 1987-04-28 1987-04-28

Country Status (1)

Country Link
JP (1) JPS63171846U (en)

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