JPS63138746U - - Google Patents

Info

Publication number
JPS63138746U
JPS63138746U JP1987032172U JP3217287U JPS63138746U JP S63138746 U JPS63138746 U JP S63138746U JP 1987032172 U JP1987032172 U JP 1987032172U JP 3217287 U JP3217287 U JP 3217287U JP S63138746 U JPS63138746 U JP S63138746U
Authority
JP
Japan
Prior art keywords
host computer
abnormality detection
detection circuit
abnormality
xon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987032172U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987032172U priority Critical patent/JPS63138746U/ja
Publication of JPS63138746U publication Critical patent/JPS63138746U/ja
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Input From Keyboards Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案を実施した端末機器の構成を表わす
図である。 1……異常検出回路、2……リレー、T……ト
ランジスタ、L……コイル、D1,D2……ドラ
イバ、R1,R2……レシーバ。
The figure is a diagram showing the configuration of a terminal device implementing the present invention. 1... Abnormality detection circuit, 2... Relay, T... Transistor, L... Coil, D1, D2... Driver, R1, R2... Receiver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ホスト計算機に接続されXON/XOFFプロ
トコルによつて通信を行なう端末機器において、
自分自身の異常を検出する異常検出回路と、この
異常検出回路の異常検出出力によつて前記ホスト
計算機から伝送されるデータを前記ホスト計算機
ヘループバツクするスイツチ手段とを設けたこと
を特徴とする端末機器。
In terminal equipment that is connected to a host computer and communicates using the XON/XOFF protocol,
A terminal device characterized in that it is provided with an abnormality detection circuit that detects an abnormality in itself, and a switch means that loops back data transmitted from the host computer to the host computer based on the abnormality detection output of the abnormality detection circuit. .
JP1987032172U 1987-03-05 1987-03-05 Pending JPS63138746U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987032172U JPS63138746U (en) 1987-03-05 1987-03-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987032172U JPS63138746U (en) 1987-03-05 1987-03-05

Publications (1)

Publication Number Publication Date
JPS63138746U true JPS63138746U (en) 1988-09-13

Family

ID=30838596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987032172U Pending JPS63138746U (en) 1987-03-05 1987-03-05

Country Status (1)

Country Link
JP (1) JPS63138746U (en)

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