JPH0270251U - - Google Patents
Info
- Publication number
- JPH0270251U JPH0270251U JP14766188U JP14766188U JPH0270251U JP H0270251 U JPH0270251 U JP H0270251U JP 14766188 U JP14766188 U JP 14766188U JP 14766188 U JP14766188 U JP 14766188U JP H0270251 U JPH0270251 U JP H0270251U
- Authority
- JP
- Japan
- Prior art keywords
- connector
- buffer
- terminal
- potential
- external device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第1図は本考案の一実施例を示す回路図、第2
図は本考案の他の実施例を示す回路図である。
1……装置本体、2,7,9,10……コネク
タ、3……信号ライン、4,5……バツフア、6
……外部装置、8……ケーブル、12,18……
制御ライン、13,15,16,17,19,2
0……コネクタの端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention. 1... Device body, 2, 7, 9, 10... Connector, 3... Signal line, 4, 5... Buffer, 6
...External device, 8...Cable, 12, 18...
Control line, 13, 15, 16, 17, 19, 2
0... Connector terminal.
Claims (1)
するためのコネクタを有し、該コネクタと接続さ
れている内部信号ラインにイネーブル端子付のバ
ツフアを介挿して成る装置において、前記イネー
ブル端子を制御ラインにより前記コネクタの第1
の端子に接続し、前記バツフアをデイスエーブル
にする第1電位に前記制御ラインを抵抗を介して
接続し、且つ、前記バツフアをイネーブルにする
第2電位を前記コネクタの第2の端子に接続する
と共に、前記コネクタと結合される前記外部装置
もしくは前記ケーブルのコネクタにおいて、前記
第1及び第2の端子に対応する2つの端子を接続
したことを特徴とするバツフア制御装置。 (2) 外部装置を直接又はケーブルを介して結合
するためのコネクタを有し、該コネクタと接続さ
れている内部信号ラインにイネーブル端子付のバ
ツフアを介挿して成る装置において、前記イネー
ブル端子を制御ラインにより前記コネクタに接続
し、前記バツフアをデイスエーブルにする第1電
位に前記制御ラインを抵抗を介して接続すると共
に、前記制御ラインと接続される前記外部装置の
端子を、前記バツフアをイネーブルにする第2電
位に接続したことを特徴とするバツフア制御装置
。[Claims for Utility Model Registration] (1) It has a connector for connecting an external device directly or via a cable, and a buffer with an enable terminal is inserted into the internal signal line connected to the connector. In the apparatus, the enable terminal is connected to a first terminal of the connector by a control line.
connecting the control line via a resistor to a first potential that connects to a terminal of the connector and disables the buffer, and connects a second potential that enables the buffer to a second terminal of the connector; . A buffer control device, wherein two terminals corresponding to the first and second terminals are connected in a connector of the external device or the cable coupled to the connector. (2) In a device that has a connector for connecting an external device directly or via a cable, and a buffer with an enable terminal is inserted into the internal signal line connected to the connector, the enable terminal is controlled. The control line is connected via a resistor to a first potential that is connected to the connector by a line and that disables the buffer, and a terminal of the external device connected to the control line is connected to a first potential that enables the buffer. A buffer control device characterized in that it is connected to a second potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14766188U JPH0270251U (en) | 1988-11-11 | 1988-11-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14766188U JPH0270251U (en) | 1988-11-11 | 1988-11-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0270251U true JPH0270251U (en) | 1990-05-29 |
Family
ID=31418271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14766188U Pending JPH0270251U (en) | 1988-11-11 | 1988-11-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0270251U (en) |
-
1988
- 1988-11-11 JP JP14766188U patent/JPH0270251U/ja active Pending
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