JPH0216571U - - Google Patents
Info
- Publication number
- JPH0216571U JPH0216571U JP9408488U JP9408488U JPH0216571U JP H0216571 U JPH0216571 U JP H0216571U JP 9408488 U JP9408488 U JP 9408488U JP 9408488 U JP9408488 U JP 9408488U JP H0216571 U JPH0216571 U JP H0216571U
- Authority
- JP
- Japan
- Prior art keywords
- terminal block
- control signals
- control
- external line
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Multi-Conductor Connections (AREA)
- Connections Arranged To Contact A Plurality Of Conductors (AREA)
Description
第１図は本考案の一実施例の概略構成図、第２
図は第１図の回路図、第３図は本考案の他の実施
例の概略構成図、第４図は第３図の回路図、第５
図は従来の制御信号の接続回路図である。
１：密閉ケース、２：回路保護抵抗、３：プリ
ント基板、５：ケーブルリード、６：雄形多芯コ
ネクタ、８：制御装置、１０：雌形多芯コネクタ
、２０，３０：外線端子台ユニツト。
Figure 1 is a schematic configuration diagram of one embodiment of the present invention;
Figures are the circuit diagram of Figure 1, Figure 3 is a schematic diagram of another embodiment of the present invention, Figure 4 is the circuit diagram of Figure 3, and Figure 5 is the circuit diagram of Figure 3.
The figure is a conventional control signal connection circuit diagram. 1: Sealed case, 2: Circuit protection resistor, 3: Printed circuit board, 5: Cable lead, 6: Male multicore connector, 8: Control device, 10: Female multicore connector, 20, 30: External line terminal block unit .
Claims (1)
される制御装置を有する制御盤において、前記制
御信号を導入する外線ケーブルが接続されるブロ
ツク端子台と、前記ブロツク端子台の背面に設け
られ前記制御盤内に取付けられる密閉ケース内に
収容され前記制御信号の電圧をそれぞれ抑制して
前記制御装置に出力する多数の回路保護抵抗とを
一体的に構成しユニツト化したことを特徴とする
外線端子台ユニツト。 In a control panel having a control device controlled by a large number of control signals introduced from the outside, a block terminal block to which an external line cable for introducing the control signals is connected, and a control panel provided on the back of the block terminal block. An external line terminal block unit comprising a plurality of circuit protection resistors which are housed in a sealed case and which suppress voltages of the control signals and output them to the control device. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9408488U JPH0216571U (en) | 1988-07-18 | 1988-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9408488U JPH0216571U (en) | 1988-07-18 | 1988-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216571U true JPH0216571U (en) | 1990-02-02 |
Family
ID=31318579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9408488U Pending JPH0216571U (en) | 1988-07-18 | 1988-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216571U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS576174B2 (en) * | 1977-12-19 | 1982-02-03 | ||
| JPS57119487A (en) * | 1981-01-19 | 1982-07-24 | Hitachi Ltd | Repeating terminal base |
-
1988
- 1988-07-18 JP JP9408488U patent/JPH0216571U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS576174B2 (en) * | 1977-12-19 | 1982-02-03 | ||
| JPS57119487A (en) * | 1981-01-19 | 1982-07-24 | Hitachi Ltd | Repeating terminal base |
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