JPH0382934U - - Google Patents
Info
- Publication number
- JPH0382934U JPH0382934U JP14350889U JP14350889U JPH0382934U JP H0382934 U JPH0382934 U JP H0382934U JP 14350889 U JP14350889 U JP 14350889U JP 14350889 U JP14350889 U JP 14350889U JP H0382934 U JPH0382934 U JP H0382934U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clock
- generating
- switching means
- driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000010587 phase diagram Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図は本考案の位相比較回路の一実施例の構
成を示す回路図、第2図及び第3図は第1図の実
施例の動作を説明するタイミングチヤート、第4
図は第1図の実施例の最短周期の入力データの両
エツジを検出する原理を説明するタイミングチヤ
ート、第5図は第1図の実施例のゲインの特性図
、第6図は従来の位相比較回路の一例の構成を示
す回路図、第7図及び第8図は第6図の例の動作
を説明するタイミングチヤートである。
1……生成回路、2……駆動回路、11乃至1
3,31,32……ラツチ回路。
FIG. 1 is a circuit diagram showing the configuration of one embodiment of the phase comparator circuit of the present invention, FIGS. 2 and 3 are timing charts explaining the operation of the embodiment of FIG. 1, and FIG.
The figure is a timing chart explaining the principle of detecting both edges of input data with the shortest period in the embodiment of Fig. 1, Fig. 5 is a gain characteristic diagram of the embodiment of Fig. 1, and Fig. 6 is a conventional phase diagram. A circuit diagram showing the configuration of an example of the comparison circuit, and FIGS. 7 and 8 are timing charts explaining the operation of the example shown in FIG. 6. 1... Generation circuit, 2... Drive circuit, 11 to 1
3, 31, 32...Latch circuit.
Claims (1)
を生成するためにスイツチングされる少なくとも
1つのスイツチング手段と、 前記入力データと、前記入力データの前記クロ
ツクのタイミングでラツチした第1の信号とから
第2の信号を生成する第1の手段と、 前記第1の信号と、前記第1の信号を前記クロ
ツクのタイミングでラツチした第3の信号とから
第4の信号を生成する第2の手段と、 前記第2の信号、第4の信号及びクロツクから
、前記スイツチング手段を駆動する信号を生成す
る第3の手段とを備える位相比較回路。[Claims for Utility Model Registration] At least one switching means that is switched to generate a signal corresponding to a phase difference between input data and a clock; a first means for generating a second signal from the first signal; and a fourth signal from the first signal and a third signal obtained by latching the first signal at the timing of the clock. A phase comparison circuit comprising: second means for generating a signal for driving the switching means; and third means for generating a signal for driving the switching means from the second signal, the fourth signal and a clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14350889U JPH0382934U (en) | 1989-12-12 | 1989-12-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14350889U JPH0382934U (en) | 1989-12-12 | 1989-12-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0382934U true JPH0382934U (en) | 1991-08-23 |
Family
ID=31690277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14350889U Pending JPH0382934U (en) | 1989-12-12 | 1989-12-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0382934U (en) |
-
1989
- 1989-12-12 JP JP14350889U patent/JPH0382934U/ja active Pending
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