JPH03110664U - - Google Patents
Info
- Publication number
- JPH03110664U JPH03110664U JP1674490U JP1674490U JPH03110664U JP H03110664 U JPH03110664 U JP H03110664U JP 1674490 U JP1674490 U JP 1674490U JP 1674490 U JP1674490 U JP 1674490U JP H03110664 U JPH03110664 U JP H03110664U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- peak
- signal
- pulse
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Description
第１図及び第２図はこの考案の一実施例を示す
図で、第１図は回路構成を示すブロツク図、第２
図は第１図の各部の信号波形の一例を示すタイミ
ングチヤート、第３図は従来の復調回路の回路構
成を示すブロツク図、第４図及び第５図はそれぞ
れ第３図の各部の信号波形を示すタイミングチヤ
ートである。
２１……増幅器、２２……交差同期パルス作成
回路、２３……ピーク検出回路、２４……Ｆ／Ｆ
回路。
Figures 1 and 2 are diagrams showing one embodiment of this invention, with Figure 1 being a block diagram showing the circuit configuration, and Figure 2 being a block diagram showing the circuit configuration.
The figure is a timing chart showing an example of the signal waveform of each part in Fig. 1, Fig. 3 is a block diagram showing the circuit configuration of a conventional demodulation circuit, and Figs. 4 and 5 are the signal waveforms of each part in Fig. 3, respectively. This is a timing chart showing the following. 21...Amplifier, 22...Cross synchronous pulse generation circuit, 23...Peak detection circuit, 24...F/F
circuit.
Claims (1)
するピーク検出回路と、 このピーク検出回路で検出した入力信号のピー
クに同期したパルス信号を作成するパルス作成回
路と、 このパルス作成回路で作成されたパルス信号が
入力されＰＷＭ信号のデータ復調信号を出力する
フリツプフロツプ回路と を具備したことを特徴とする復調回路。[Scope of claim for utility model registration] A peak detection circuit that detects the peak of an input signal and holds the peak; A pulse generation circuit that creates a pulse signal synchronized with the peak of the input signal detected by this peak detection circuit; 1. A demodulation circuit comprising a flip-flop circuit which receives a pulse signal created by a pulse creation circuit and outputs a data demodulated signal of a PWM signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1674490U JPH03110664U (en) | 1990-02-23 | 1990-02-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1674490U JPH03110664U (en) | 1990-02-23 | 1990-02-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110664U true JPH03110664U (en) | 1991-11-13 |
Family
ID=31520000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1674490U Pending JPH03110664U (en) | 1990-02-23 | 1990-02-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110664U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015200744A (en) * | 2014-04-07 | 2015-11-12 | キヤノン株式会社 | Belt conveying device and image forming apparatus |
-
1990
- 1990-02-23 JP JP1674490U patent/JPH03110664U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015200744A (en) * | 2014-04-07 | 2015-11-12 | キヤノン株式会社 | Belt conveying device and image forming apparatus |
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