JPS6374835U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIGS. 2 to 5 are waveform diagrams of the device shown in FIG. 1, FIG. 6 is an explanatory diagram of the encoder, and FIGS. 7 and 8 are Waveform diagrams when the encoder rotates clockwise and counterclockwise, Figure 9 is a configuration diagram of the conventional device, Figure 1
0 and 11 are explanatory diagrams of the operation of the conventional device.

Claims (1)

[Claims for Utility Model Registration] A first one-shot circuit that detects a rising edge of one input signal of a two-phase pulse signal and generates a pulse signal; A first one-shot circuit that detects a falling edge of said one input signal and generates a pulse signal. a first D-type flip-flop whose clock input is the signal generated by the first one-shot circuit and whose D input is the other input signal of the two-phase pulse signal; the signal generated by the second one-shot circuit; a second D-type flip-flop whose clock input is the D-type flip-flop, and whose D-type input signal is the other input signal; third and fourth one-shot circuits that generate delayed pulses after eliminating the superposition when the pulse superimposition circuit detects superposition of the output signal, and when the pulse superposition circuit does not detect superposition of the output signal, the first one-shot circuit a first logic circuit that selects the third one-shot circuit and outputs the first output signal when the pulse superimposition circuit detects superposition of the output signal; a second logic circuit which selects the fourth one-shot circuit and outputs a second output signal by selecting the fourth one-shot circuit when superimposition is detected.