JPH02103924U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a synchronizing signal generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing A to A in FIG.
A voltage waveform diagram showing the state of point G, Fig. 3 is a block diagram showing a conventional synchronizing signal generation circuit, and Fig.
FIG. 3 is a waveform diagram showing the states of points A to C in the figure. DESCRIPTION OF SYMBOLS 1...First pulse generator, 2...First clock pulse generation circuit, 3...Second clock pulse generation circuit, 4...Second pulse generator, 5...First flip-flop, 6...Second flip-flop, 7
...AND gate.

Claims (1)

[Claims for Utility Model Registration] A first pulse generator 1 that repeatedly generates a first pulse, and a second pulse whose width is larger than that of the first pulse than the period of the first pulse. a second pulse generator 4 that generates a clock pulse with a long period; a first clock pulse generator circuit 2 that generates a first clock pulse in synchronization with the leading edge of the first pulse; and a trailing edge of the first pulse. a second clock pulse generation circuit 3 that generates a second clock pulse in synchronization with the first clock pulse;
a first flip-flop 5 that reads the pulses of the clock; and a first flip-flop 5 that reads the pulses of the first
a second flip-flop 6 for reading the output of the flip-flop 5; and a logic gate 7 for obtaining an AND output of the first pulse and the output of the second flip-flop 6.