JPH02103924U - - Google Patents

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Publication number
JPH02103924U
JPH02103924U JP13795188U JP13795188U JPH02103924U JP H02103924 U JPH02103924 U JP H02103924U JP 13795188 U JP13795188 U JP 13795188U JP 13795188 U JP13795188 U JP 13795188U JP H02103924 U JPH02103924 U JP H02103924U
Authority
JP
Japan
Prior art keywords
pulse
flop
flip
clock
generates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13795188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13795188U priority Critical patent/JPH02103924U/ja
Publication of JPH02103924U publication Critical patent/JPH02103924U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係わる同期信号発
生回路を示すブロツク図、第2図は第1図のA〜
G点の状態を示す電圧波形図、第3図は従来の同
期信号発生回路を示すブロツク図、第4図は第3
図のA〜C点の状態を示す波形図である。 1…第1のパルス発生器、2…第1のクロツク
パルス発生回路、3…第2のクロツクパルス発生
回路、4…第2のパルス発生器、5…第1のフリ
ツプフロツプ、6…第2のフリツプフロツプ、7
…ANDゲート。
FIG. 1 is a block diagram showing a synchronizing signal generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing A to A in FIG.
A voltage waveform diagram showing the state of point G, Fig. 3 is a block diagram showing a conventional synchronizing signal generation circuit, and Fig.
FIG. 3 is a waveform diagram showing the states of points A to C in the figure. DESCRIPTION OF SYMBOLS 1...First pulse generator, 2...First clock pulse generation circuit, 3...Second clock pulse generation circuit, 4...Second pulse generator, 5...First flip-flop, 6...Second flip-flop, 7
...AND gate.

Claims (1)

【実用新案登録請求の範囲】 第1のパルスを繰返して発生する第1のパルス
発生器1と、 前記第1のパルスよりも幅が大きい第2のパル
スを前記第1のパルスの周期よりも長い周期で発
生する第2のパルス発生器4と、 前記第1のパルスの前縁に同期して第1のクロ
ツクパルスを発生する第1のクロツクパルス発生
回路2と、 前記第1のパルスの後縁に同期して第2のクロ
ツクパルスを発生する第2のクロツクパルス発生
回路3と、 前記第1のクロツクパルスに同期して前記第2
のパルスを読み込む第1のフリツプフロツプ5と
、 前記第2のクロツクパルスに同期して前記第1
のフリツプフロツプ5の出力を読み込む第2のフ
リツプフロツプ6と、 前記第1のパルスと前記第2のフリツプフロツ
プ6の出力との論理積出力を得るための論理ゲー
ト7と から成る同期信号発生回路。
[Claims for Utility Model Registration] A first pulse generator 1 that repeatedly generates a first pulse, and a second pulse whose width is larger than that of the first pulse than the period of the first pulse. a second pulse generator 4 that generates a clock pulse with a long period; a first clock pulse generator circuit 2 that generates a first clock pulse in synchronization with the leading edge of the first pulse; and a trailing edge of the first pulse. a second clock pulse generation circuit 3 that generates a second clock pulse in synchronization with the first clock pulse;
a first flip-flop 5 that reads the pulses of the clock; and a first flip-flop 5 that reads the pulses of the first
a second flip-flop 6 for reading the output of the flip-flop 5; and a logic gate 7 for obtaining an AND output of the first pulse and the output of the second flip-flop 6.
JP13795188U 1988-10-21 1988-10-21 Pending JPH02103924U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13795188U JPH02103924U (en) 1988-10-21 1988-10-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13795188U JPH02103924U (en) 1988-10-21 1988-10-21

Publications (1)

Publication Number Publication Date
JPH02103924U true JPH02103924U (en) 1990-08-17

Family

ID=31399845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13795188U Pending JPH02103924U (en) 1988-10-21 1988-10-21

Country Status (1)

Country Link
JP (1) JPH02103924U (en)

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