JPS61189624U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, FIG. 2 is a waveform diagram showing signals T ₁ to Tn shown in FIG. 1, and FIG. 3 is a synchronous circuit 2-- shown in FIG. 1.
FIG. 4 is a waveform diagram of each part of the circuit shown in FIGS. 1 and 3. 2-1 to 2-N...Synchronization circuit (detection signal output circuit), 6...Timing pulse generator, 15...
OR gate (detection signal output circuit), T ₁ to Tn...
...signal (timing pulse signal), _Q1 to Qn...
...signal (edge detection signal).

Claims (1)

[Scope of utility model registration request] a timing pulse generator that outputs a plurality of timing pulse signals having different output timings and that do not overlap; and a timing pulse generator that makes each of the timing pulse signals correspond one-to-one for each of the plurality of input pulses, and which one of the input pulse signals and a detection signal output circuit that outputs an edge detection signal having a pulse width of the timing pulse during a period in which the corresponding timing pulse signal becomes active for the first time when the edge becomes active level. Multiple pulse edge synchronization circuit.