JPH0436318U

JPH0436318U -

Info

Publication number: JPH0436318U
Application number: JP7901490U
Authority: JP
Priority date: 1990-07-25
Filing date: 1990-07-25
Publication date: 1992-03-26

Description

[Brief explanation of the drawing]

第１図は本考案の周波数掃引発信器の構成ブロ
ツク図、第２図は第１図において示した周期設定
部及び周波数設定部を抽出して示した構成ブロツ
ク図、第３図は本考案の周波数掃引発生器の動作
を説明するためのタイミングチヤートである。１……第１のデジタル加算器、２……正弦波デ
ータメモリ、３……ＤＡ変換器、４……ＬＰＦ、
５……周期設定部、６……周波数設定部、６１…
…第２のデジタル加算器、６２……第３のデジタ
ル加算器。 Fig. 1 is a block diagram of the structure of the frequency sweep oscillator of the present invention, Fig. 2 is a block diagram of the structure extracting the period setting section and frequency setting section shown in Fig. 1, and Fig. 3 is the block diagram of the frequency sweep oscillator of the present invention. This is a timing chart for explaining the operation of a frequency sweep generator. 1... First digital adder, 2... Sine wave data memory, 3... DA converter, 4... LPF,
5... Cycle setting section, 6... Frequency setting section, 61...
...Second digital adder, 62...Third digital adder.

Claims

[Claims for Utility Model Registration] (1) A first digital adder that adds input frequency setting data and feedback output data every basic clock; and a first digital adder that adds the input frequency setting data and feedback output data; a sine wave data memory from which amplitude data is read every time a basic clock is input as an address; a DA converter that converts the digital signal of the amplitude data outputted from the sine wave data memory into an analog signal; an LPF for removing harmonics from the output signal of the first digital adder; a cycle setting unit that counts a set cycle using the most significant bit output from the first digital adder as a clock; a frequency setting section that adds a constant phase to the frequency setting data for each cycle and outputs the result to the first digital adder using a timing clock generated by counting the cycles of the frequency setting data; The frequency setting data of the digital adder No. 1 is made variable in the frequency setting section for each period set by the period setting section, so that the frequency can be arbitrarily swept. sweep oscillator. (2) The frequency setting section includes a second digital adder that adds the input step frequency setting data and the feedback output data for each timing clock generated by the MSB and outputs the result as step frequency data. and a third digital addition that adds the start frequency data and the step frequency data from the second digital adder for each of the timing clock signals and outputs the result to the first digital adder as frequency setting data. Claim (1) characterized in that it is constituted by:
) frequency sweep oscillator.