JPS6045512U - Sine wave signal generation circuit - Google Patents
Sine wave signal generation circuitInfo
- Publication number
- JPS6045512U JPS6045512U JP13783983U JP13783983U JPS6045512U JP S6045512 U JPS6045512 U JP S6045512U JP 13783983 U JP13783983 U JP 13783983U JP 13783983 U JP13783983 U JP 13783983U JP S6045512 U JPS6045512 U JP S6045512U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- sine wave
- counter
- wave signal
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Of Color Television Signals (AREA)
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は近似サイン波の波形図、第２図はサイン波発生
のための基本的なブロック図、第３図は本考案の９０°
位相差のあるサイン波発生回路のブロック図である。
１ ： １／２分周器、２，７：カウンタ、３：メモリ
、５，８：データ・ラッチ回路、４，９：Ｄ／Ａ変換器
、６：デコーダ。Figure 1 is a waveform diagram of an approximate sine wave, Figure 2 is a basic block diagram for generating a sine wave, and Figure 3 is a 90° waveform diagram of the present invention.
FIG. 2 is a block diagram of a sine wave generation circuit with a phase difference. 1: 1/2 frequency divider, 2, 7: counter, 3: memory, 5, 8: data latch circuit, 4, 9: D/A converter, 6: decoder.
Claims (1)
ット入力とするカウンタと、該カウンタ出力をアドレス
信号とし対応アドレスに記憶されているサイン波信号の
各点のデータを順次読み出すメモリと、該メモリ出力を
アナログ値に変換するＤ／Ａ変換器で構成され、近似的
に１／２ｆｖ（垂直同期周波数）の今イン波信号を発生
するサイン波発生回路において、上記カウンタの出力ア
ドレス信号と９０°の位相差を持つアドレス信号を発生
するカウンタを新たに設け、該両アドレス信号で上記メ
モリより９０°゛の位相差を持つ２つのサイン波を発生
することを特徴とするサイン波信号発生回路。A counter that uses a horizontal synchronization signal as a clock input and a vertical synchronization signal as a reset input, a memory that uses the counter output as an address signal and sequentially reads out data at each point of a sine wave signal stored at a corresponding address, and the memory output. In the sine wave generation circuit, which is composed of a D/A converter that converts the signal into an analog value, and which generates a current-in wave signal of approximately 1/2 fv (vertical synchronization frequency), the output address signal of the counter and the 90° A sine wave signal generating circuit characterized in that a counter for generating address signals having a phase difference is newly provided, and two sine waves having a phase difference of 90° are generated from the memory using the two address signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13783983U JPS6045512U (en) | 1983-09-07 | 1983-09-07 | Sine wave signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13783983U JPS6045512U (en) | 1983-09-07 | 1983-09-07 | Sine wave signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6045512U true JPS6045512U (en) | 1985-03-30 |
Family
ID=30309473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13783983U Pending JPS6045512U (en) | 1983-09-07 | 1983-09-07 | Sine wave signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045512U (en) |
-
1983
- 1983-09-07 JP JP13783983U patent/JPS6045512U/en active Pending
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