JPS6046600U - Audio signal processing device - Google Patents

Audio signal processing device

Info

Publication number
JPS6046600U
JPS6046600U JP1983139466U JP13946683U JPS6046600U JP S6046600 U JPS6046600 U JP S6046600U JP 1983139466 U JP1983139466 U JP 1983139466U JP 13946683 U JP13946683 U JP 13946683U JP S6046600 U JPS6046600 U JP S6046600U
Authority
JP
Japan
Prior art keywords
read
counter
signal
amplitude
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983139466U
Other languages
Japanese (ja)
Inventor
三晴 清彦
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP1983139466U priority Critical patent/JPS6046600U/en
Publication of JPS6046600U publication Critical patent/JPS6046600U/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の音声信号処理装置の構成例を示すブロッ
ク図、第2図は第1図に示した装置の説明に供する線図
、第3図は本考案による音声信号処理装置の一実施例を
示すブロック図、第4間尺    ゛び第5図は本考案
の説明に供する波形図である。 4は制御回路、5及び6はメモリ、10はパルス発生器
、12はA/D変換器、16は書込みカウンタ、20及
び21はD/A変換器、25は振幅制御回路、26は可
変分周器、27及び32はエンコーダ、29及び31は
第1及び第2の読出しカウンタ、33はタイミングパル
ス発生回路である。
FIG. 1 is a block diagram showing a configuration example of a conventional audio signal processing device, FIG. 2 is a diagram for explaining the device shown in FIG. 1, and FIG. 3 is an implementation of the audio signal processing device according to the present invention. A block diagram showing an example, and FIGS. 4 and 5 are waveform diagrams for explaining the present invention. 4 is a control circuit, 5 and 6 are memories, 10 is a pulse generator, 12 is an A/D converter, 16 is a write counter, 20 and 21 are D/A converters, 25 is an amplitude control circuit, and 26 is a variable component. 27 and 32 are encoders, 29 and 31 are first and second read counters, and 33 is a timing pulse generation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 音声信号を1対のメモリに一定周期で交互に書込むと共
に、上記1対のメモリから上記一定周期で交互に読出す
ようにした音声信号処理装置において、所望周波数の読
出しクロックを得る読出しクロック発生手段と、該読出
しクロックが供給される第1及び第2の読出しカウンタ
並びに同期分配手段と、該同期分配手段の複数の出力の
振幅を制御する振幅制御手段とを有し、上記第1の読出
′   しカウンタは上記一定周期の最初から読出しを
開始し、上記第2の読出しカリンクは上記第1の読出し
カウンタを基準として動作を開始して上記一定周期の終
りに上記メモリからの読出しを完了し、上記同期分配手
段は上記第1の読出しカウンタの読出した第1の読出し
信号と上記第2の読出しカウンタの読出した第2の読出
し信号とを同期分配し、上記振幅制御手段は上記第1及
び第2の読出し信号が共存する期間に上記第1の読出し
信号の振幅を漸減させると共に、上記第2の読出し信号
の振幅を漸増させるようにしたことを特徴とする音声信
号処理装置。      ゛
In an audio signal processing device that alternately writes audio signals into a pair of memories at a constant cycle and alternately reads audio signals from the pair of memories at a constant cycle, a read clock is generated to obtain a read clock of a desired frequency. means, first and second read counters to which the read clock is supplied, synchronous distribution means, and amplitude control means for controlling the amplitude of a plurality of outputs of the synchronous distribution means, ' The counter starts reading from the beginning of the fixed period, and the second reading counter starts operating based on the first reading counter, and completes reading from the memory at the end of the fixed period. , the synchronous distributing means synchronously distributes the first read signal read by the first read counter and the second read signal read by the second read counter, and the amplitude control means synchronously distributes the first read signal read by the first read counter and the second read signal read by the second read counter. An audio signal processing device characterized in that the amplitude of the first read signal is gradually decreased and the amplitude of the second read signal is gradually increased during a period in which the second read signal coexists.゛
JP1983139466U 1983-09-08 1983-09-08 Audio signal processing device Pending JPS6046600U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983139466U JPS6046600U (en) 1983-09-08 1983-09-08 Audio signal processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983139466U JPS6046600U (en) 1983-09-08 1983-09-08 Audio signal processing device

Publications (1)

Publication Number Publication Date
JPS6046600U true JPS6046600U (en) 1985-04-02

Family

ID=30312583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983139466U Pending JPS6046600U (en) 1983-09-08 1983-09-08 Audio signal processing device

Country Status (1)

Country Link
JP (1) JPS6046600U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123007A (en) * 1977-04-01 1978-10-27 Nec Corp Sound synthesizer of element editing type
JPS5648880A (en) * 1979-07-20 1981-05-02 Hauni Werke Koerber & Co Kg Receiving station of air force type conveying zone for conveying rod like article in tobacco processing machine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123007A (en) * 1977-04-01 1978-10-27 Nec Corp Sound synthesizer of element editing type
JPS5648880A (en) * 1979-07-20 1981-05-02 Hauni Werke Koerber & Co Kg Receiving station of air force type conveying zone for conveying rod like article in tobacco processing machine

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