JPS58220534A - Synchronizing pulse extracting circuit - Google Patents

Abstract

PURPOSE:To make it unnecessary to provide such parts as a resistance, a capacitor, etc. having high accuracy, which are required for PLL, and to simplify the adjustment, an also to extract quickly a synchronizing pulse, by checking a synchronization shift of the synchronizing pulse and a receiving signal whenever a rise point of the receiving signal comes, so that synchronization is taken by correcting a period of the synchronizing pulse in accordance with magnitude of its synchronization shift. CONSTITUTION:In case when a receiving signal S1 is fairly delayed, and a variation point A1 is generated when a count value of a control counter 17 is 14, a corrected value X and the final value N become 2 and 17, respectively, a synchronizing pulse SP rises when the count value of the control counter 17 is varied to ''0'' from 17, and the final value N is returned to 15 again. Subsequently, when the count value of the control counter 17 is changed to 8 from 7, the synchronizing pulse SP falls. If a variation point A2 is generated when the count value of the control counter 17 is ''1'', the corrected value X and the final value N become -2 and 13, respectively, in accordance with which the synchronizing pulse SP falls when the count value of the control counter 17 is varied to 7 from 6, and rises when it is varied to ''0'' from 13. In this way, the synchronization is taken by this correction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization pulse extraction circuit that extracts synchronization pulses from digital signals based on the NBZ method, NRZi method, or the like.

In order to process digital signals transmitted by the NRZ method or NRZi method on the receiving side,
It is necessary to extract the synchronization pulse from the received signal.

Conventionally, when extracting a synchronization pulse from this type of digital signal, a synchronization pulse extraction circuit using a PLL (phase-locked loop) is often used. 1st
The figure is a block diagram showing an example of a synchronization pulse extraction circuit using a conventional PLL. The circuit shown in this figure extracts synchronization pulses from an N│2 digital signal.

In this figure, the bit change point of the NZ digital signal is detected as a shift point by the differentiating circuit 2, and the output of the differentiating circuit 2 is rectified by the rectifier 3, thereby converting the NRZ digital signal. All deviation points are output as positive pulses.

The output of the rectifier 3 is supplied to a phase detector 4, where the phase is compared with the output of a CO (voltage controlled oscillator) 6, and the phase difference is output to the next filter 5 as a phase difference signal. f) The phase difference signal from which the cylindrical frequency component has been removed by the filter 5 controls vCO 6 so that the oscillation frequency of the VCU 6 becomes the same as the input signal frequency of the phase detector 4 . Then, the output of VCO6 is used as a synchronization pulse.
By the way, in such a conventional synchronization pulse extraction circuit, it is necessary for the PLL to be in a phase-locked state, and for this reason, many adjustment pulses (for example, 1o) that change regularly in the initial state are required.

The disadvantage was that it required input of pulses (on the order of pulses). Furthermore, in the synchronous pulse extraction circuit described above, P
Since LL was used, there was also the disadvantage that highly accurate parts were required and adjustment was difficult.

In view of the above iC situation, this invention eliminates the need for parts such as high-precision resistors and capacitors required for PLL, is easy to set up, and enables quick synchronization pulse extraction (synchronization pulse extraction circuit It provides:

To achieve this objective, a synchronous pulse extraction circuit according to the present invention comprises: 1. Synchronization is achieved by checking the synchronization pulse and the received signal every time the rising point of the received signal arrives, and correcting the cycle of the synchronization pulse according to the magnitude of the synchronization difference. It counts the clock pulses that it has and clears it when it takes the final value.
A control counter that repeatedly counts up again, a correction value creation circuit that determines a correction value according to the value of the control counter at the time the received signal rises, and a correction value that is added to the normal final value of 15 for correction. A final value counter that is used as the final value after the final value, a 4-bit comparator that outputs a signal when the count value of the control counter becomes equal to 1/2 of the final value stored in the final value counter, and It outputs a signal when the value becomes equal to the final value, and
a 5-bit comparator that clears the control counter with this signal and loads the final value counter again with the normal final value of 15;
It is equipped with an S flip-flop (output FF) that is set by the output signal of the 5-bit comparator and reset by the output signal of the 4-bit comparator, and extracts the synchronization pulse from the output terminal of this output FF. 2 〇 An actual example of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment according to the present invention. In the figure, a received signal S is supplied to a change point detection circuit 12 via a receiving terminal 11. In FIG. Of the positive and negative pulses obtained by differentiating the received signal S, the changing point detection circuit 12 outputs only the positive pulse St as a changing point pulse. Change point pulse S! is supplied to the set terminal S of the FF (flip-flop) 13 during correction, the load terminal LD of the correction counter 14, and the trigger terminal T of the sign determination FF 15.

FF13 during correction is a 几S flip-flop,
It is set by the rising edge of the changing point pulse S, and outputs a signal HNB (“1# signal”) from its output terminal Q, and supplies it to the correction counter 14 and the final value counter 16.

The correction counter 14 is a hexadecimal down counter, and the change point pulse S! When is applied to the load terminal LD, the data Y output from the correction value generation circuit 21 is loaded, and the clock pulse CP is counted down while being enabled by the signal ENB+ using this as an initial value. Then, a borrow signal B is output by the clock pulse CP that is applied when the current (+MO) is applied.The borrow signal B resets ppxa during correction, and
Rub the output with #05. The sign determination FF 15 is a D-type flip-flop, and its output signal 8N is supplied to the up/down terminal U/D of the final value counter 6.

The final value counter 6 is a 32-ary counter, is enabled by the signal gNB supplied from the FF 13 during correction, and counts clock pulses CP. In this case, the signal 8N supplied to the up/down terminal U/D
If is "1", count up, and if it is 20#, count down. Then, counting continues until the signal 13NB becomes 0# and the enable is released. Also,
11M [15J is supplied to the data input terminal, and when the #1# signal is applied to the load terminal 11.
Shift "15" is loaded into the final 1 shift counter 61, and the count value is set to the normal final value [15J.

Furthermore, from the output terminal of the final value counter 6, each digit of the count value is 20.21.2! , 21.2' Ic corresponding 5-bit output signals CA, CB, Go, CD.

CB is being output.

Next, 17 is a 32-decimal control counter that counts up the clock pulse cp of a constant period supplied to the clock terminal CK, and counts up 5 bits corresponding to each digit 2°12'#2"?28.244. The signal QA * QB eQo, Qv
, Qm are output. Further, 18 is a 5-bit comparator which is cleared by the signal U supplied from the clear terminal CLR+, and the signal QA-Ql supplied from the control counter 17 and the signal supplied from the final value counter 16. It constantly compares CA-xCm and outputs a signal U when both are equal. Next, 19 is a 4-bit comparator, and each input terminal (signal Q input to QD from the control counter 17, final value counter 1.6 to No. 18 CB-
A signal of each 4 bits of CB is supplied, and when the two values are equal, a signal V is output.0 Also, the output B'F20
is set at the falling edge of the signal U, and reset at the falling edge of the signal ■. A synchronizing pulse SP is then taken out from the output terminal Q of the output FF 20.

By the way, final 1i! When rNJ is output from the counter 16, the control counter 17 outputs the clock pulse CP.
is repeatedly counted as 0, 1...N, 0.1...N, and the synchronization pulse SP rises every time the count value changes by 01 from the final 1[iN, so the period of the synchronization pulse SP is
The period is (N+1) times the period of the clock pulse CP. Therefore, when synchronization is achieved, the final value N = 15,
The period of the synchronization pulse is kept constant at the normal period, that is, 16 clock pulses, and when synchronization is achieved, this final value N
By correcting the value of and changing the period of the synchronizing pulse SP, synchronization can be achieved.

The correction value creation circuit 21 is a circuit that creates a correction value X for correcting this final value N, and changes point pulse S!
Creates a positive or negative correction value X as described below based on the value of the control counter 17 each time
The created correction value
5'', and load the corrected fi final value N=15+X into the final value counter 16 (this is used to adjust the period of the synchronization pulse 8P.For example, when the correction value X=-2, the corrected fi final value N=15+X The final value of N=15-2=13, and the period of the synchronization pulse SP is 14@1 of the period of the clock pulse CP.
This will happen. In this way, the period of the synchronization pulse SP after correction increases or decreases by the amount of the clock pulse corresponding to the correction value X.

Hereinafter, the correction value will be explained based on FIG. 3.

3 shows the count value of the control counter 17, which normally repeats a count of 0, 1...15, 0, 1...15. Then, the synchronous clock 8P falls when the count value of the control counter 17 changes from 7 to 8.
As mentioned above, it rises when changing from 15 to 0.

Next, Fig. 3 @ is a waveform diagram when the receiving @ polarization signal S1 and the synchronizing pulse SP are in a synchronized state, and the rising edge of the receiving (fi times signal) and the falling point B of the synchronizing pulse SP are aligned. θ in Fig. 3 shows the synchronization pulse SP with respect to the received prime signal Sl.
is delayed by about 5 clock pulses CP,
In this case, it is necessary to significantly shorten the period of the synchronizing pulse SP to recover from the delay. Therefore, the correction value X is set by 12 times. @3 Figure @ is for the received signal Sl,
The synchronization pulse SP has advanced by about six clock pulses, and in this case, the correction value X is set to +2 in order to significantly extend the period of the synchronization pulse SP and delay its advance. In Fig. 3, the synchronization pulse SP is slightly delayed (about 2 clock pulses) with respect to the received signal S.
In this case, synchronization can be achieved by shortening the period of the synchronization pulse SP a little, so the correction value is set to 5--1. In Fig. 3, the synchronizing pulse SP is slightly advanced (about one crotter pulse) relative to the received signal S. In this case, synchronization can be achieved by extending the period of the synchronizing pulse SP a little. Set the correction value to +1. In this way, the correction (I
IiX becomes 1::1 when the changing point A precedes the falling point B, that is, when the count value of the control counter 17 is from 0 to 7, it becomes negative, and when the changing point A lags the falling point B. That is, when the count value of the control counter 17 is between 8 and 15, it becomes positive. Furthermore, the absolute +1lfY of the correction value It was determined as shown in Table 1 according to the count value (see Figure 3). In addition, Qo, QD in Table 1
is the output signal of the bit corresponding to the second digit of the count value of the control counter 17, and the correction j[X is created based on this.

Table 1:,゛・11 That is, in order to actually create the correction 1i1tX shown in Table 1, the correction value creation circuit 2'1 takes the exclusive OR of the signals Qd and QD, and when the sum is 11', (This is the absolute value of the correction value Y=2. When the sum is “θ”, Y=1. Also, the sign of the correction value X is negative when the signal QD is ・O#, and negative when the signal QD is Since it is positive when QD, it can be obtained from the signal QD.

Next, the operation of this embodiment will be explained with reference to the waveform diagram in FIG. This waveform diagram shows the case where the rising point of the receiving 1d signal occurs when the count 1licA=14.

When a received signal S is supplied to the receiving terminal 11 in FIG. 2 and its rising point is detected by the changing point detection circuit 12I, a changing point pulse S1 is output (as shown in FIG. 4). As a result, the FF13 during correction is set and the output signal ffNB
is supplied to each IN terminal of the correction counter 14 and the final value counter 16 to enable both counters 14 and 16 (the fourth
figure@).

Further, the change point pulse S, is also supplied to the load terminal LD of the correction counter 14, and the absolute value Y= of the correction j[X=2 (see the first group) corresponding to the count value 14 of the control counter 17 at this time. 2 is loaded into the correction counter 14 as the initial count value (FIG. 4 - ). Further, the change point pulse S is supplied to the trigger terminal T of the sign determination FF15,
The value of the signal QD at this point is ``1'' (the count value of the control counter 17 is 14, so the signal Qn is 1') and the sign judgment FF
Set to 15. Then, the output terminal Q of the sign determination FF
, a signal 8N with a value of 11' is supplied to the up/down terminal U/D+ of the final value counter 16.
6 is ready to count up.

Next, when the clock pulse CP shown in FIG.
, the count value of the control counter 17 becomes 1.
From 4 to 15, the count value of the correction counter 14 changes from 2 to 11, and the count value of the final value counter 16 changes from 15 to 1.
(See Fig. 4 @, ■, θ) The O-th chlorant value is 16, the count 1 of the correction counter 14 is OG, and the count value of the final value counter 16 is 17.
It changes respectively. And clock pulse CP3
is supplied to each of the clock terminals CK, a borrow signal B (as shown in FIG. 4) is output from the borrow terminal B of the correction counter 14.
is output, and upon its rise, the correction FF 13 is reset and the signal gNB becomes #01 (Fig. 4 @) o This releases the enable of both the correction counter 14 and the final value counter 16, and the clock pulse CPs Even if it goes down, the correction counter is no longer 14. IIl, the value of the closing price counter 16 does not change (θ in FIG. 3). In this way, the final value N=17 is stored in the final value counter 16,
Only the count value of control counter 17 changes to 17.

When the count value of the control counter 17 reaches 17, the 5-bit I word Qm~Qm and the C person~CI supplied to the 5-bit comparator 181 both become "17" and are equal. Comparator 18 outputs signal U. ,
And Iki-go U's voice power FF20E-t at the fall!
' and the synchronizing pulse S taken out from its output terminal Q.
At the same time as raising P, the control counter 17 is cleared and its count flu is set to 0. Also, load the first shift "15" into the final first shift counter 16 and set the final value N to "15" again.
◎In this way, the period of the synchronizing pulse SP is extended by two clock pulses, and the correction is completed. Then, the count value of the control counter 17 increases to 0.1...? 1
If 17 is taken, the 4-bit signals Q-Qn and CB-Cm supplied to the 4-bit comparator 19 are both "7".
Then, the signal V is output. The signal V resets the output FF20 at its fall, and this causes the synchronization pulse S
P falls (see Figure 4 ■, ■).

Next, the situation in which synchronization is actually achieved by such correction will be explained with reference to FIG. 5. FIG. 5 shows the received signal 8. When there is no distortion, this indicates a situation in which the synchronization pulse SP gradually becomes synchronized from an unsynchronized state. In the figure, an arrow P indicates a synchronization point (that is, a point at which the synchronization pulse SP falls and the received signal S should rise when synchronization is established). First, if the rising point A1 of the received signal S, occurs when the count value of the control counter 17 is 2, then the changing point pulse S! is output and the FF is being corrected.
13, and the signal h2NB becomes 11'. This enables the correction counter 14 and the final value counter 16, and further sets the absolute value Y=2 of the correction value X=-2 in the correction counter 14. Also, at this time, the signal Q
Since n is 10#, the output signal 8 of sign determination FF15
N also becomes "0.", and the final value counter 16 prepares to count down.Then, the clock pulse CP is applied to each clock terminal CK of the correction counter 14 and the final value counter 6.
is applied twice, then the count value of the correction counter 14 becomes O,! The count value of the closing price counter 16 becomes 13.

When the next clock pulse is applied, a borrow signal B is output from the correction counter 14, and at the rising edge of the borrow signal B, the FF 13 during correction is reset. With these settings, when the count value of the control counter 17 increases by 61, it becomes 4.
Direct input signals QA-QD and CB-Ci of the bit comparator 19
Both a becomes 6, and a signal V is output. Then, the signal ■ resets the output FF20 at the falling edge, and the synchronization pulse 8
Lower P. Next, when the count value reaches 13, the signal U is output from the 5-bit comparator 18 ◎The signal U sets the output FF 20 at the rising edge, raises the synchronization pulse SP, and sets the final value counter 16 to the normal final value 15. and also clears the control counter 17. In this way, the period of the synchronization pulse SP is shortened by two clock pulses. From then on, the synchronization pulse SP falls when the count value CA changes from 7 to 8, corresponding to the normal final value 15. , the operation of rising when changing from 15 to 0 is repeated.

Next, change point A! The count value of the control counter 17 is 4.
If it occurs at the time of , the correction f direct Correction value X according to count +1 (rsJ)
=-1, and the period of the synchronizing pulse SP is shortened by one clock pulse in the same way as described above.

In this way, the period of the synchronizing pulse SP is corrected little by little each time the correction is made, and as shown in Figure 5, the synchronization is gradually achieved. is when the change point occurs at count value 0 or 15 of the control counter 7, so synchronization can be achieved by shifting by 7 clock pulses.In this case, the correction value ±2→±1→±1
→±1, so if there is no distortion in the received signal, synchronization will definitely be achieved if the change point A is received five times.

FIG. 6 is a diagram showing a situation in which the received signal S1 is initially synchronized (despite this, distortion occurs in the received signal S1, and then synchronization is achieved again. In the figure, the arrow P indicates the synchronization point. , the received signal 5t11 is considerably delayed and the change point AI occurs when the count face of the control counter 7 is 14. As already explained, the correction value X is 2. The final 1 straight N is 17. Therefore hand,
The synchronization pulse SP is generated when the count value of the control counter 17 is 1.
It rises when changing from 7 to 0, and the final value N is 15 again.
Return to i,ru. Then, when the count value of the control counter 17 changes from 7 to 8, the synchronizing pulse SP falls.As a result, the auxiliary pulse SP follows the received signal 8.G and becomes out of synchronization.

Falling when the runt value changes from 7 to 8, from 15 to 0
(When this change occurs, the rising operation is repeated. Then, when the count value of the control counter 17 is 1, a change occurs, the correction 1@X=2w falls at the final rise, and the change from 13 to 01 occurs. stand up when

This correction thus allows synchronization (see FIG. 6).

Note that in the second embodiment, the clock pulse CPI
Although a frequency 16 times that of the synchronizing pulse 8P was used here, it is also possible to use a frequency range 32 times or 8 times that of the synchronizing pulse 8P.

In the embodiment, the correction value X is -2, -1°+1.
Although it was created so as to take each fil of +2, it is also possible to create it so that it takes different values.

As described above, the synchronous pulse extraction circuit according to the present invention includes a control counter that counts clock pulses having a constant period, clears them when a predetermined value (final value) is taken, and repeats up-counting, and a received signal. A correction value creation circuit that determines a correction value according to the value of the control counter at the time when the rising edge occurs, a final value counter that adds this correction value to the current final value to obtain the next final value, and a control counter. a 4-bit comparator that outputs a signal when the count value of becomes equal to the final value of 172 stored in the final value counter; and a 4-bit comparator that outputs a signal when the value of the control counter becomes equal to the final value; This signal clears the control counter and loads the final value counter with the value 15, and R8 is set by the output signal of the 5-bit comparator and reset by the output signal of the 4-bit comparator. Since the device is equipped with a flip-flop (output FF) and the synchronous clock pulse is extracted from the output terminal of the output FF, the following effects can be obtained.

(2) Even if the received signal and the synchronization pulse are out of synchronization, the synchronization pulse changes by the correction 11 and becomes synchronized, so that synchronization can be achieved quickly.

Furthermore, since the period of the synchronizing pulse is kept at the normal length when no received signal is received, and gradually changed when a received signal is received, it has an effect similar to the locking function of a PLL circuit.

- Since a PLL circuit is not used, and digital parts that are easy to adjust are used, adjustment is easy and parts such as fleas, highly accurate resistors, and capacitors are not required.

[Brief explanation of the drawing]

Claims (1)

[Scope of Claims] A synchronization pulse extraction circuit that extracts a synchronization pulse from a digital signal supplied in a bit serial manner, comprising: (1) detecting means for detecting a change point of the digital signal and outputting a change point pulse based on the change point; ■ A @1 counter that constantly counts clock pulses of a constant period; ■ A compensation 3/1/1 direct generation circuit that generates a correction value based on the count value of the first counter when the change point pulse is output; ■ a second counter that sets and stores a final value of the first counter based on the correction value; and ■ the first counter.
When the count value of the counter becomes equal to the final value stored in the second counter, the signal 'IpJ1 is outputted, and the counter M1 is cleared by the first signal of III, and a predetermined value is (1) when the count value of the first counter becomes 1/2 of the final value stored in the second counter; Second
(1) a flip-flop that is set by the first signal and reset by the second signal; and a synchronizing pulse is output from the output terminal of the flip-flop. Take it out! ! ! Synchronous pulse extraction circuit with f mold.