JPH0323009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a sine wave generation circuit that obtains a sine wave output synchronized with an input waveform.

(Prior Art) As a conventional circuit for synchronizing the input square wave and the output of the sine wave generating circuit in this manner, there is a circuit shown in FIG. 4. The variable frequency divider circuit 1 is set so that the clock from the input terminal 5 is N times the square wave input. The output of the variable frequency dividing circuit 1 is supplied to an N-stage stepped pseudo sine wave generating circuit 2. On the other hand, the synchronization circuit 3 compares the phase of the square wave from the input terminal 6 and the sine wave output of the pseudo sine wave generation circuit 2, and when the phase of the square wave is ahead, the phase of the square wave from the variable frequency divider circuit 1 is Make the cycle rate lower than the set value,
Furthermore, when the phase of the square wave is delayed, the phase is matched by stopping the count of the variable frequency divider circuit 1 once.

This circuit has the following problems.

1) Since the phase is matched while comparing each output cycle, it takes time to synchronize.

2) The synchronization circuit complicates the circuits for comparing phases, changing the frequency division number of the variable frequency divider circuit, and stopping at 1 o'clock.

3) To simplify the circuit, if the basic clock is corrected one by one for each period, it will take synchronization time, and the value set to 1 should not be set close to the frequency of the input square wave in advance. cannot be corrected.

4) If the amount of correction at one time is increased, high synchronization accuracy cannot be obtained.

(Object of the invention) The object of the invention is to solve such problems,
To provide a sine wave generating circuit capable of forming a sine wave synchronized with a square wave within a frequency range with a frequency difference of 2 to 3% using a relatively simple circuit and with an arbitrary phase difference.

(Structure of the Invention) The sine wave generating circuit of the present invention includes a differentiating circuit that differentiates an input square wave, a variable frequency dividing circuit that provides a predetermined delay to the output pulse of this differentiating circuit, and an output of this variable frequency dividing circuit. a fixed frequency divider circuit which is reset by a predetermined frequency divider and outputs a rectangular wave having a reference frequency; and a variable frequency divider circuit which forms a stepped sine wave according to the output of this fixed frequency divider circuit The circuit includes a pseudo sine wave generation circuit that is reset by the output, and a filter that extracts the output frequency component of the pseudo sine wave generation circuit.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
Figures a to f are time charts for explaining the operation of Figure 1, and Figures 3a, b, and c are output waveform diagrams of Figure 1. In the figure, reference numeral 2 denotes an N-stage pseudo sine wave generating circuit, which generates a step-like sine wave of one period with N clock inputs. Further, the frequency dividing circuit 10 has an input terminal 5
By dividing the basic clock from the square wave input frequency, a clock having a frequency N times the frequency near the center of the range of possible values of the square wave input frequency is output.

A differentiating circuit consisting of two D flip-flops 11 and 12 and an OR gate 13 detects the rising edge of the square wave input from the terminal 6 (FIG. 2a) and outputs a pulse (FIG. 2b). With this output (differential) pulse, the counter 14 starts counting the clock input and counts a set constant number of basic clocks, and this circuit corresponds to a variable frequency divider circuit that delays the differential pulse. After counting (FIG. 2c), the output of the D flip-flop 16 is set to a high level "1", and at the same time the basic clock gate 15 is closed to stop counting. The D flip-flops 16, 17 and the OR gate 18 detect the output from the counter 14 and generate a pulse (FIG. 2d).
And the pseudo sine wave generating circuit 2 is reset. The frequency dividing circuit 10 starts counting from this reset point (Fig. 2 e), and the counter in the pseudo sine wave generating circuit 2 is also reset, so after being reset, the counter starts counting as shown in Fig. 2 f. The same waveform is always output. Therefore, these circuits 10, 2
is reset after a certain period of time from the rise of the square wave input, so the phase difference between the input square wave and the output sine wave is always constant. The phase difference is determined by the count of the counter 14. This counter 1
By making the count number 4 variable, it is possible to phase synchronize the input square wave and the output staircase wave with an arbitrary delay.

Figures 3a, b, and c are output waveform diagrams of Figure 1. When the center frequency and square wave input frequency are the same, the waveform perfectly matches the period of the staircase wave as shown in Figure 3a. When the square wave input frequency is higher than the center frequency, the waveform becomes like a staircase wave with the last end suddenly missing, as shown in Figure 3b, and when the square wave input frequency is lower than the center frequency, the waveform becomes like a third step wave. As shown in Figure c, the end of the staircase wave becomes low level "0" for a time that is less than the period of the square wave.

The staircase wave thus obtained can be given a sine waveform by attaching a simple filter 3 or a capacitor to the output of the pseudo sine wave generating circuit 2.

(Effects of the Invention) As explained above, the present invention makes it possible to synchronize the phase of the output with the input square wave using a simple circuit, and also allows the mutual delay amount to be arbitrarily set. This also has the effect of being able to synchronize the phases without a special control circuit even when changes occur.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2a
~f is the timing chart in Fig. 1, Fig. 3a,
b and c are waveform diagrams showing three examples of the output waveforms in FIG. 1, and FIG. 4 is a circuit diagram of a conventional sine wave generating circuit. In the figure: 1...Variable frequency divider circuit, 2...Pseudo sine wave generation circuit, 3...Synchronization circuit, 4...Filter, 5...Clock input terminal, 6...Square wave input terminal, 7...
Output terminal, 10... Frequency dividing circuit, 11, 12, 1
6, 17...D flip-flop, 13, 15,
18...OR gate, 14...delay counter.

Claims (1)

[Claims] 1. A differentiating circuit that differentiates the input square wave, a variable frequency dividing circuit that provides a predetermined delay to the output pulse of this differentiating circuit, and a reference clock that is reset by the output of this variable frequency dividing circuit and divides the predetermined clock. a fixed frequency dividing circuit that outputs a rectangular wave of a frequency, and a pseudo sine wave generating circuit that forms a stepped sine wave according to the output of the fixed frequency dividing circuit and is reset by the output of the variable frequency dividing circuit. , and a filter for extracting the output frequency component of the pseudo sine wave generation circuit.