JPS62271517A - N-phase pulse generator - Google Patents

Abstract

PURPOSE:To generate pulses in n-phase formed by accurate by and equally dividing into n-part without any hindrance even if the repetitive period is dissident by always dividing digitally one period of an input signal into (n)-part. CONSTITUTION:A 3-phase clock generator 1 being an n-phase pulse generator converts a clock signal into 3-phase clock signals CK1-CK3 synchronously with a signal fed to an input terminal, the signals CK1-CK3 are counted by counters 2a-2c and the count is latched digitally in latch circuits 3a-3c. The counters 2a-2c and the circuit 3a-3c are reset by the input signal and an output of the circuits 4a-4c is inputted to latch circuits 4a-4c. Further, the output data of the circuits 4a-4c is read as a preset value by using the counters 5a-5c to count the original clock by the number of read values. In counting the clock signal, 3-phase pulses phiR-phiB are outputted to control an analog switch thereby outputting a color signal.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention is directed to the use of rectangular wave signals having a constant repetition period.
This relates to a circuit that accurately divides the period into n equal parts and generates n-phase pulses. Conventional technology Generally speaking, as a method of multiplying a rectangular wave signal by n to generate n-phase pulses, the phase shown in Fig. 3 is used.・2 ・・
- There is a method using a locked loop (PLL) circuit or a filter circuit shown in FIG.

The method using a PLL circuit includes a phase comparator 20, a low-pass
Filter 21, voltage controlled oscillator 22.1/n frequency divider 2
4 generates a rectangular wave with a frequency n times synchronized with the phase of the rectangular wave signal applied to the input terminal 25, and by dividing this rectangular wave signal by 1/n, the output terminal 27, n-phase pulses φ1 to φ. This is what you get.

Further, in the method using a filter circuit, a bandpass filter 28 extracts an n-times harmonic frequency component from a rectangular wave signal applied to the input terminal 31, and a waveform shaping circuit 29 shapes this signal into a rectangular wave. , 1/n The frequency is divided by the frequency divider 3o, and the n-phase pulses φ1 to φ are sent to the output terminal 33.

This is what you get.

Problems to be Solved by the Invention In the above-mentioned conventional example, the problems will be explained with reference to FIGS. explain. The rectangular wave input signals applied to input terminals 26 and 31 are converted into rectangular wave multiplied signals having a frequency three times the input signal frequency and appear at terminals 26 and 32 provided in the middle of each circuit.

Furthermore, regarding the phase, the phase of the input signal and the phase of the multiplied signal should be synchronized.

However, if the period of the input signal is not constant and the period fluctuates beyond the tracking range of the PLL, the phases of the input signal and the multiplied signal cannot be synchronized, causing a phase shift as shown by the broken line in FIG. Also, in the case of a filter, if the period fluctuation width exceeds the pass frequency bandwidth of the filter, especially if only one period fluctuates significantly, the phase cannot follow the fluctuation. It disappears.

As a result, a three-phase pulse φ1. φ2. The rising timing of φ3 is 11,
As shown in 12.13, it becomes non-uniform, and 1 of the input signal a
It is not possible to obtain the timing to accurately divide the cycle into three equal parts.

Means for Solving the Problems The present invention provides means for digitally measuring the period of the input signal using an n-phase clock signal that repeats the period of the input signal at a period much shorter than the period. The number of phase clocks is temporarily stored, and the original clock signal used to generate the n-phase clock signal is measured by a separately provided measuring means, and the clock signal for each of the stored n-phase clocks is measured. By providing a frequency dividing means for outputting one pulse, it is possible to generate n-phase pulses by accurately dividing the period of the input signal into n equal parts.

Operation By means of the above-described means, one period of the input signal is always digitally divided into n equal parts, and even if the period is non-uniform, exactly n-phase pulses can be generated without any problem.

Embodiment As an embodiment of the present invention, a three-phase pulse generator for obtaining the application timing of R, G, and B color signals in a beam index type image display device will be explained.

FIG. 1 is a block 6 page diagram for explaining this embodiment. In the figure, reference numeral 1 indicates three-phase clock signals CK1, CK2, . It is a three-phase clock generator that converts to CK3.

2a, 2b, 2c are three-phase clock signals CK1°CK2
．． This counter is used to count CK3 and is reset by an input signal. 3a, sb.

3C is a latch for digitally temporarily storing the counter output value. Also 4a, 4b.

4C is a similar latch. And 5a, sb.

5C is a counter that reads latched data as a preset value and generates an output pulse when the original clock signal is counted by the number of the preset values. This output pulse is a three-phase pulse, and if this three-phase pulse is used as a switching strobe pulse for the analog switch 6, the RIG and B video signals can be converted into serial color signals.

The detailed operation will be described below with reference to the signal timing diagram shown in FIG. Three-phase clock CK1. generated by three-phase clock generator 1. CK2. CK3 is counted by counters 2a, 2b, and 2c, respectively, to count the number of input signals in one cycle. In Figure 2, CK 1 cuff, cK
2. Each cK3 cut counts as 6. This counted value is stored and held in the latches 3a, 3b, and 3c at the rising edge of the next input signal pulse. At this time, the pulses generated by the counter 6 and decoder 7 are simultaneously latched or loaded into the latches 4a, 4b, 4a, and counter 5a. counter 5a
raises the ripple carry (RC) output at this point and starts counting from the clock signal immediately after this,
Count 7 clocks, which is the loaded value, and RC
C Withdrawal is cancelled. Then, this falling edge is converted into a narrow pulse by the differentiating circuit 8a and applied to the load terminal of the counter 5b.The counter 5b starts counting and counts 6 clocks, which is the loaded value. Then, RCC withdrawal is stopped.Similarly, counting starts from this point, and RC is stopped at the 6th clock.The point to note here is that the falling of RC of counter 7 is as follows. This is the 19th clock from the start of counting of the counter 5a, which is equal to the number of clocks in the first cycle of the input signal.In other words, one cycle of the input signal is tH: t: tB =
Three-phase pulse φR roughly divided into three equal parts: 7:6:6
This means that 1φG and φB were generated.

In this example, the division ratio was chosen to be 7:6:6 in order to demonstrate the error caused by this method.
This error is one clock at most, and can be reduced to a negligible value by increasing the clock frequency.

The above operation is similarly repeated for another period of the input signal, but as mentioned earlier, the width of one period is non-uniform. Therefore, if a period narrower than the previous period continues, the value held in latch 3C will change to the next value before the RC output of counter 5C has finished falling, so another stage of latch 4C is provided. It is. The same applies to latches 4a and 4b.

As described above, R in the beam index type image display device
, G, and B color signals, using a three-phase pulse generator as an example.
It is no secret that it can be developed into phase pulse generation.

Effects of the Invention As described above, the present invention measures one period of a rectangular wave signal digitally using an n-phase clock signal, and by means of multiplying the signal, it is possible to always accurately measure one period even if the repetition period is uneven. Divide into n equal parts. Can generate n-phase pulses,
This is the R, G of the beam index type image display device.
, as a strobe signal at the application timing of the B color signal, it is possible to display an image without color shift.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a three-phase pulse generator that is an embodiment of the present invention, Fig. 2 is a signal timing diagram for explaining its operation, and Figs. 3 and 4 are conventional n-phase pulse generators. A block diagram of the generator, FIG. 5, is a signal timing diagram to explain their operation. 9'・・1...Three-phase clock generator, 2a to 2c, 5a
~5C...Counter, 3a~3c, 4a~4C
...Latch circuit, 9...Analog switch.

Claims (1)

[Claims] means for digitally measuring one cycle of a rectangular wave signal using an n-phase clock signal having a frequency much higher than the repetition frequency of the rectangular wave signal; 1. An n-phase pulse generator, comprising means for measuring an original clock signal to be generated, and generating n-phase pulses obtained by dividing one period of the rectangular wave signal into n equal parts.