JPH07101845B2 - Digital phase lock loop device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital phase-locked loop device in which a phase-locked loop is composed of digital circuit elements.

BACKGROUND ART In recent years, many types of digital phase-locked loop devices have been announced. This digital phase-locked loop device consists of a digital circuit element in the phase-locked loop. Compared to the analog method, it is less likely to have variations due to the parts used, and the desired characteristics can be obtained without adjustment. There are advantages. On the other hand, the digital phase-locked loop device generally divides the output of the fixed oscillator into a loop output, and therefore the phase of the phase is limited to an input frequency which is less than a few tenths of the maximum operating frequency of the logic circuit element used therein. I couldn't get the lock loop to work.

Further, when the input frequency is increased, the division ratio is reduced, that is, the quantization is roughened, which leads to the deterioration of the loop characteristic. In particular, in a digital phase-locked loop device for an input frequency that is a fraction of the maximum operating frequency of the logic circuit element, the characteristics of the logic circuit element itself, especially the delay characteristics, have a large effect in addition to the effect of the quantization error. It is difficult to adopt the configuration.

FIG. 3 shows an example of a conventional phase-locked loop device for an input of a fraction of the frequency of a conventional fixed oscillator (OSC) 4 (that is, 1 / N when N is a positive integer). . The phase difference between the input signal PBSG and the phase locked loop clock signal PLLCK is detected as the count value of the counter 1.

The clock pulse MCK output from the fixed oscillator 4 is shown in FIG. 4 (1), the input signal PBSG is shown in FIG. 4 (2), and the phase-locked loop clock signal PLLCK is shown in FIG. 4 (3). Has been done. D-type flip-flop (DFF)
The signal A from the output terminal of No. 3 is shown in FIG.

The AND gate G1 has a clock pulse MCK and an input signal PBSG.
Then, the output signal A of the D-type flip-flop 3 is given, and the output of the AND gate G1 is inputted to the clock input terminal CK of the counter 1. The output signal CNTOUT of the counter 1 is shown in FIG. 4 (5).

The output signal U of the frequency divider 7 is given to the clock input terminal CK of the D-type flip-flop 8 and to the clock input terminal CK of the D-type flip-flop 3 via the inverting circuit N1, and further the phase-locked loop clock signal PLLCK
Is derived as

The output of the AND gate G2 is given to the counter 1 and the register 5 as the reset signal RESET. This reset signal RE
SET is as shown in FIG. 4 (6). In FIG. 4, a phase difference is generated for the time from the rising time a of the input signal PBSG to the rising time b of the phase-locked loop clock signal PLLCK, and this time is measured by the counter 1 based on the clock pulse MCK. .

In the AND gate G1 before the clock input of the counter 1, the input signal P BSG, the output signal A of the D-type flip-flop 3 which latches the input signal P BSG at the rising edge of the phase-locked loop clock signal PLLCK, and the clock pulse MCK of the fixed oscillator 4 are input. The counter 1, which is provided and by which the output of the AND gate G1 is provided, counts from the time points a to b. The counter 1 counts the pulse from the AND gate G1 until the reset signal RESET from the other AND gate G2 is input.

The output from the terminal Q of another D-type flip-flop 8 which further latches the output from the terminal Q of the D-type flip-flop 3 at the rising edge of the signal U, and the D-type flip-flop 3
The output from the terminal Q of is given to the AND gate G2, and this A
At the rising edge of the reset signal RESET from the ND gate G2, the signal CNTOUT representing the count value of the counter 1 is latched in the register 5.

After that, the counter 1 is reset in response to the reset signal RESET, is set by the next rising edge of the input signal PBSG, and the next counting operation is started. The phase difference signal I output from the register 5 is shown in FIG.
This is given to the decoder 6 and decoded. The load signal E output from the decoder 6 is as shown in FIG. 4 (8), and is loaded into the frequency divider 7 as the value of the frequency division ratio of the frequency divider 7.

Thus, the clock pulse MCK of the fixed oscillation circuit 4 is divided by the value represented by the phase difference signal I between the input signal PBSG and the face-locked loop clock signal PLLCK to generate the phase-locked loop clock signal PLLCK. By changing the frequency division ratio of the device 7, the phase of the input signal PBSG and the phase of the phase-locked loop clock signal PLLCK are kept in agreement.

The frequency divider 7 divides the frequency by N when the input signal PBSG and the phase-locked loop clock signal PLLCK are in phase, and the frequency division ratio of the frequency divider 7 is N + depending on the magnitude of the phase difference.
1 or N-1, etc., and the phases are matched. For example, the function of the decoder 6 with N = 8 is to decode into the load signal E of the frequency divider 7 in order to obtain the frequency division ratio of the frequency divider 7 corresponding to the phase difference signal I.

The load signal E representing the frequency division ratio given from the decoder 6 to the frequency divider 7 is loaded into the frequency divider 7 in response to the load clock signal F. The load clock signal F is supplied to the logic circuit 9 when the output signal U of the frequency divider 7 has a specific value.
Is generated as shown in FIG. 4 (9). In FIG. 4, N = 8, and since the phase difference between the time points a and b occurs, the load signal E for dividing by 9 is applied from the decoder 6 to the frequency divider 7 at the time point c, and the phase difference is given at the time point d. Corrected to zero.

Problems to be Solved by the Invention In the prior art shown in FIGS. 3 and 4 as described above, if the input signal PBSG has a certain period as shown in FIG. You can take action. However, if the input signal PBSG has a modulated waveform as shown in FIG.
The PBSG cycle changes in length. The phase-locked loop clock signal PLLCK at this time is shown in FIG. 5 (2), and when a phase difference occurs, it may be corrected by the length of the cycle of the input signal PBSG.

FIG. 5 (3) shows the output signal A of the D flip-flop 3.
FIG. 5 (4) shows the output signal CNTOUT of the counter 1, FIG. 5 (5) shows the reset signal RESET, and FIG.
FIG. 6 shows the phase difference signal I output from the register 5,
FIG. 5 (7) shows a load signal E representing the frequency division ratio of the decoder 6.
5 (8) shows the load clock signal F from the logic circuit 9. In FIG. 5, the phase difference at the time point a1 is similarly corrected at the time points b1, c1, d1.
Then, the phase becomes opposite polarity, which adversely affects the phase-locked loop characteristic.

It is an object of the present invention to appropriately correct the division ratio of a division cycle even if the cycle of the input signal changes so that the phase of the phase-locked loop clock signal can match the input signal. It is to provide a lock loop device.

Means for Solving the Problems The present invention includes a fixed oscillator (4) and a first D-type flip-flop (3) for reading an input signal (PBSG) at the time of receiving a phase-locked loop clock signal (PLLCK, U). , A frequency divider (7) that divides a clock pulse (MCK) from a fixed oscillator (4) to generate a phase-locked loop clock signal (PLLCK, U), and a divider that sets a value of a predetermined division ratio. In response to the frequency ratio setting means (12), the clock pulse (MCK) from the fixed oscillator (4), the input signal (PBSG), and the output (A) of the first D-type flip-flop (3), Counter means (G1,1) for counting clock pulses (MCK) by a number corresponding to the phase difference between the input signal (PBSG) and the phase-locked loop clock signal (PLLCK, U), and a first D-type flip-flop (3) Output (Q) of the phase locked loop clock signal. (PLLCK, U) and read no second form flip-flop (8) upon receipt of the output of the first and second 2D-type flip-flop (3, 8) (Q,
In response to Q), a reset signal generating means (G2) for resetting the counter means (G1,1) is provided, and a signal (F) is output for each cycle of the phase-locked loop clock signal (PLLCK, U). The reset signal (RESS) from the reset circuit generating means (G2) and the logic circuit (9) for setting the frequency division ratio of the frequency divider (7).
ET) causes one stable state (S), and the output signal (F) of the logic circuit (9) causes the other stable state (R).
In response to the RS type flip-flop (10) and the output (Q) of the RS type flip-flop (10), the frequency divider (7) controls the counter means (G1, A switching means (11) for giving a signal representing a frequency division ratio corresponding to the output of 1) and for providing the output of the frequency division ratio constant setting means (12) in the other stable state (R). It is a digital phase lock loop device.

Operation According to the present invention, when a phase difference between the input signal PBSG and the phase-locked loop clock signal PLLCK, U occurs, the amount of the phase difference is output from the fixed oscillator 4 until reset by the counter means G11. The clock pulse MCK is counted and detected, and the frequency division ratio corresponding to the counted value is set, and thereafter, the frequency divider 7 is set at the value of the predetermined frequency division ratio set by the frequency division ratio constant setting means 12. Divide by. This makes it possible to minimize the phase shift between the input signal and the phase locked loop clock signal.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. This embodiment is partially similar to the configuration shown in FIG. 3 above, and corresponding parts bear the same reference numerals. The clock pulse MCK from the fixed oscillator 4 is generated as shown in FIG. 2 (1) and input to the AND gate G1. The input signal PBSG has the waveform shown in FIG. 2 (2), is applied to the input terminal D of the D flip-flop 3, and
It is given to the AND gate G1. D-type flip-flop 3
When the phase-locked loop clock signal PLLCK is input to the clock input terminal CK, it derives the logical value given to the input terminal D to the output terminal Q, and outputs the signal A from the inverting output terminal.

The output signal A of the D-type flip-flop 3 is given to the AND gate G1. The output of AND gate G1 is counter 1.
Entered in. Output signal A of D-type flip-flop 3
Is as shown in FIG. 2 (4). The counter 1 counts the pulses given through the AND gate G1, and the count value is the output signal shown in Fig. 2 (5).
It is given to the register 5 as CNTOUT.

The output signal W of the frequency divider 7 is derived as the phase-locked loop clock signal PLLCK via the inverting circuit N1 and is also input to the clock input terminal CK of the other D-type flip-flop 8. The signal at the output terminal Q of the D-type flip-flop 3 is input to the input terminal D of the D-type flip-flop 8 and also given to the AND gate G2. The signal from the output terminal Q of the D flip-flop 8 is also given to the AND gate G2. Output of AND gate G2 is counter 1
Is input as the reset signal RESET and is given to the register 5.

When the output of the AND gate G2 is input, the register 5 stores the output signal CNTOUT of the counter 1 and derives the phase difference signal I to the decoder 6. The reset signal RESET output from the AND gate G2 is as shown in FIG. 2 (6), and the phase difference signal I of the register 5 is shown in FIG. 2 (7).
Indicated by. The phase difference signal I of the register 5 is input to the decoder 6. The output E of the decoder 6 is as shown in FIG.

The output U of the frequency divider 7 is given to the logic circuit 9. The logic circuit 9 derives the load clock signal F, and this load clock signal F has the waveform shown in FIG. The frequency divider 7 receives the load signal G indicating the frequency division ratio when the load clock signal F is input, divides the clock pulse MCK from the fixed oscillator 4 by the frequency division ratio, and outputs the signal U. Derive. Thus, the decoder 6 receives the clock pulse from the fixed oscillator 4 at the time from the rising of the input signal PBSG to the rising of the phase-locked loop clock signal PLLCK.
The value obtained by counting MCK is decoded and given from the data switching circuit 11 to the frequency divider 7. A load signal G representing the frequency division ratio given from the data switcher 11 to the frequency divider 7 is shown in FIG. 2 (10), and the frequency division ratio is shown in FIG. 2 (10).

The RS flip-flop 10 is set by the output of the AND gate G2 and reset by the load clock signal F from the logic circuit 9. The signal H from the output terminal Q of the RS flip-flop 10 is as shown in FIG. 2 (11) and is supplied to the data switching circuit 11. When the signal H is at a high level, the data switching circuit 11 uses the output E from the decoder 6 as the load signal G representing the frequency division ratio and the frequency divider 7
When the signal H is at a low level, a signal representing the frequency division ratio of the predetermined constant N from the constant setting circuit 12 is given to the frequency divider 7 as the load signal G. The constant N is, for example, "8" in this embodiment.

When a phase difference occurs between the rising edge a2 of the operating input signal PBSG and the rising edge b2 of the phase-locked loop clock signal PLLCK, the clock pulse MCK from the fixed oscillation circuit 4 is input to the counter 1 via the AND gate G1. The counted signal is output and the output signal CNTOUT is given to the register 5.

When the output signal U of the frequency divider 7 rises and is input to the D-type flip-flop 8, a rising waveform of the reset signal RESET is obtained from the AND gate G2, which causes the register 5 to output the output of the counter 1 3 ”is stored, the phase difference signal D of the register 5 is supplied to the decoder 6, and the output E representing the frequency division ratio“ 9 ”is derived from the decoder 6.

The RS flip-flop 10 derives a high level signal H in response to the reset signal RESET from the AND gate G2. Therefore, the data switching circuit 11 outputs the output E from the decoder 6.
Is given as the load signal G of the frequency divider 7, and the logic circuit 9
According to the load clock signal F from 1 to 2, the frequency divider 7 is loaded at the time point c2 shown in FIG. In this way, the frequency divider 7 performs the frequency division operation at the frequency division ratio "9".

The RS flip-flop 10 is reset at the time point c2 when the load clock signal F from the logic circuit 9 falls. Therefore, the data switching circuit 11 gives the signal representing the constant N from the constant setting circuit 12 to the frequency divider 7 as the load signal G. At the time points d2 and e2 when the load clock signal F of the logic circuit 9 is derived, the frequency divider 7 is loaded with the constant N as a frequency division ratio, and the frequency division operation is performed.

In this way, after the reset signal RESET is applied from the AND gate G2, the frequency division ratio “9” for correcting the phase difference signal I representing the phase difference from the register 5 is divided during the time up to the time point c2. After that, the frequency division ratio N (= 8) when the phase difference between the signals PBSG and PLLCK is the expected value "8" is loaded into the device 7. As a result, thereafter, the phase difference between the rising edge f2 of the input signal PBSG and the rising edge g2 of the phase-locked loop clock signal PLLCK can be made as small as possible.
The problem described in connection with the figure is solved.

In the above-described embodiment, the output E from the decoder 6 is loaded into the frequency divider 7 only once when the phase difference between the input signal PBSG and the phase locked loop clock signal PLLCK is generated. As another embodiment of the present invention, after a plurality of load clock signals F of the logic circuit 9 are generated, the RS flip-flop 10 is reset so that the output E of the decoder 6 is output to the predetermined frequency divider 7 by a plurality of times. The load signal G from the data switching circuit 11 may be loaded into the frequency divider 7 after that.

Effects As described above, according to the present invention, not only is the phase of the input signal PBSG and the phase locked loop clock signal PLLCK, U advanced or delayed, but the amount of phase difference is also the counter means G1, It can be detected by 1, and the frequency division ratio of the frequency divider 7 can be changed in accordance with the amount of the difference, which can shorten the pull-in time when the phase difference such as rising is large. Excellent effect is achieved.

Moreover, in the present invention, when the phase difference occurs, the frequency division ratio by the output of the counter means G1,1 is used, and thereafter, the predetermined frequency division ratio set by the frequency division ratio constant setting means 12 is used. Frequency division by the input signal PBSG and phase locked loop clock signal PLLCK,
The phase shift with U can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a waveform diagram for explaining the operation of the embodiment shown in the figure, FIG. 3 is a block diagram of the previously proposed digital phase locked loop device, and FIGS. 4 and 5 are shown in FIG. It is a waveform diagram for explaining the operation of the digital phase-locked loop device. 1 ... Counter, 3,8 ... D flip-flop, 4 ...
... fixed oscillator, 5 ... register, 6 ... decoder, 7 ...
… Divider, 9… Logic circuit, 10… RS flip-flop, 11… Data switching circuit, 12… Constant setting circuit, G1, G
2 …… AND gate, N1 …… Inversion circuit

Claims (1)

[Claims] 1. A fixed oscillator (4), a first D-type flip-flop (3) for reading an input signal (PBSG) when receiving a phase-locked loop clock signal (PLLCK, U), and a fixed oscillator (4). A frequency divider (7) that divides the clock pulse (MCK) of to generate a phase-locked loop clock signal (PLLCK, U), and a division ratio constant setting means (12) that sets a value of a predetermined division ratio. ), The clock pulse (MCK) from the fixed oscillator (4), the input signal (PBSG), and the output (A) of the first D-type flip-flop (3) in response to the input signal (PBSG) and the phase. The counter means (G1,1) for counting the clock pulses (MCK) by the number corresponding to the phase difference with the lock loop clock signal (PLLCK, U) and the output (Q) of the first D-type flip-flop (3) Read when receiving the phase-locked loop clock signal (PLLCK, U) And the 2D-type flip-flop (8), the output of the first and second 2D-type flip-flop (3, 8) (Q,
In response to Q), reset signal generating means (G2) for resetting the counter means (G1,1) and a signal (F) for each cycle of the phase-locked loop clock signal (PLLCK, U) are output, A logic circuit (9) for setting the division ratio of the frequency divider (7) and a reset signal (RESE) from the reset signal generating means (G2).
One stable state (S) by T) and the other stable state (R) by the output signal (F) of the logic circuit (9).
In response to the RS type flip-flop (10) and the output (Q) of the RS type flip-flop (10), the frequency divider (7) controls the counter means (G1, A switching means (11) for giving a signal representing a frequency division ratio corresponding to the output of 1) and for providing the output of the frequency division ratio constant setting means (12) in the other stable state (R). And a digital phase-locked loop device.