JPS62239738A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To lower the frequency of a reference signal generating circuit by setting the frequency division ratios of the 1st and the 2nd variable frequency dividing means according to the result of phase comparison of a phase comparing means. CONSTITUTION:Edge information extracted by a D flip-flop 16 and an exclusive OR circuit 18 is supplied to CK terminals of D flip-flops 19 and 20 to latch the output of a frequency divider 15 and the Q output of the D flip-flop 19. The Q outputs of the D flip-flops 19 and 20 are supplied to a frequency division ratio setting circuit 21. The frequency division ratio setting circuit 21 outputs frequency division ratio information on the basis of the Q outputs of the D flip-flops 19 and 20. The in-phase output of a reference signal generating circuit 11 is supplied to a counter 12 and the negative-phase output is supplied to a counter 13; and overflow signals from the counters 12 and 13 are selected by a selecting circuit 14 and a selected signal is frequency-divided by the fre quency divider 15. Consequently, the frequency of a reference frequency from a reference signal generating means is lowered.

Description

[Detailed description of the invention] ke] Industrial application field The failure Ij11 is related to the hit regeneration circuit.

(b) Conventional technology Conventionally, digital phase synchronization l! ! i path @) lW7t As a clock regeneration circuit #: C1 Example is JP-A-56-1280
There are nine known devices disclosed in Japanese Patent No. 27.

This kind of conventional clock recovery circuit will be explained with reference to FIG. 4 and FIG.

8 in Fig. 4, (1) is a reference signal generating means, (2J is a force tank serving as a variable frequency dividing means for dividing the output 1s from the reference 1if signal generating circuit (1), and (3) is a force tank. Tank (2
) is a frequency divider that divides the overflow signal t2, (4) is a nine D clip-flop whose D terminal is connected to the received signal input 1 child (5), (6) is the Q output of the D flip-flop (4) An exclusive OR circuit that uses the signal from the received signal input terminal (5) as a dual input, and the D terminal of (7) is the output of the frequency divider (3).

The 7tCK terminal is connected to the output of the exclusive OR circuit (6), and the D flip-flop (8) is connected to the Q terminal of the D flip-flop (7), and the 7HCK terminal is connected to the output of the exclusive OR circuit (6).
The terminal is greatly connected to the output of the exclusive OR circuit (6).
'lI) flip-flop, <9) uD flip-flop (71 (dividing ratio setting (b) that sets the count number (i.e., frequency division ratio) of the counter (2J) based on the 9 outputs of 8J)
It is a road. still.

A phase comparator i is composed of a D flip-flop (71(8)).

About 1wJ work in a while! I! ◎ Now, assuming that the reception signal input terminal (5) L is applied with the immediate reception signal gg!1 shown in Fig. 5 (&J), this reception!+9't-D flip-flop (4 ) is applied to the received signal one bit before the previous bit and the current received signal to the exclusive OR circuit (6). , the overflow 1 word of the counter (2) to which the output No. 16 from the reference signal generation circuit (1) is stamped is the 5th word.
If this occurs as shown in Figure (dJ), the reproduced clock signal resulting from this overflow No. 11 frequency-divided by t2 will be as shown in Figure (e).JIJ5.

Such a regenerated clock signal is output from the output terminal αIL and is applied to the D flip-flop (Ω).
An exclusive OR circuit (6J) is used (see FIG. 5(e)).The latch output is latched by a D flip-flop (81) based on the edge information of the arrow.

By the way, the frequency division ratio setting circuit (9) sets the count number of the counter (2) to seven based on the latch outputs of the upper i+dD flip-flops (7) and (8).

If the Q outputs of D flip-flops (7) and (8) are both at H level, ff1J also determines that the phase of the reproduced clock is ahead of the received signal, and calculates the force Kund number (frequency division) of the counter (2). Output a signal that makes the ratio 1-N+1.

D flip flow rough (71 (8E)) If the Q output is H level, L level, or L level and B level, it is determined that the phases of the received signal and the reproduced clock match, and the counter (2) starts counting. It outputs a signal that makes the number (frequency division ratio) t-N, and when the Q outputs of D flip-flops (7) and (8) are both at L level, n is %, and the phase of the font clock is higher than the 1N signal. Determine that it is late and set the counter (2)
(3) Problems to be solved by the invention In the conventional circuit described above, the data rate of the received signal is 2Kbl.
If t/+s, then 2 KNHZ is required as the emission frequency of the reference signal generation path (1). Also.

Frequency division ratio N-1, N, N+ 10) The relationship is as follows:
(This is a balance between the time required to establish synchronization between the lr and the reproduced clock and the jitter of the reproduced clock when synchronization is established.) Generally speaking, if N's 11f'fl" is large, the less jitter the reproduced clock becomes. However, as the data rate of the received signal increases, the frequency of the reference signal generation circuit naturally increases, and there is a risk that the above-mentioned t signal processing may not be possible.

1-1 FM4-5--15-+2 Ginko l Haki Nishi In view of the above problems, the present invention includes a reference signal generating means and a first output signal from the reference signal generating means which is divided in frequency. 1st
a second variable frequency dividing means that divides the output signal of fg2 which has a phase difference of 180 degrees from the output signal of brown 1; a selection means for selecting an output; a phase comparison means for comparing n7 selected by the selection means with respect to the phase of the signal and the input signal; Frequency division ratio setting means for setting all the frequency division ratios of the variable frequency division means, and one selection state klU11il of the 8 selection means based on the signal from the frequency division ratio setting arm of Tomoko.
With the above configuration, the first and second output signals from the reference signal generating means are sent to the first and second variable frequency dividing means. The frequency is divided based on the frequency division ratio setting means output No. 1J according to the result of the comparison of the frequency division peaks and the seven phases.

(f) Embodiment FIG. 1 is a diagram showing an embodiment of the present invention. α11r! The reference signal generation circuit, @, is supplied with the positive phase output from the reference signal generation circuit l. 1 counter, 1131 is a second counter to which the negative phase output from the reference signal generation circuit tiII is supplied, α knob is Ml, and the second counter is a selection circuit that selects the 54 overflow signal, lω is a selection circuit. Frequency division a% (161 is a D flip-flop whose D1 child is connected to the signal input terminal αη, (IJI is the Q of the D flip-flop Ω ue) An exclusive IIjII circuit that uses the signals from the output and the received signal input terminal 1?), the D terminal of the μ water is the output of the frequency divider (15), and the 7tcKm child is the exclusive OR circuit u
Connected to the output of l is a ninety flip-flop.

CAuI) terminal is connected to the Q terminal of the D clip-flop (L field, and the 7jCK terminal is connected to the output of the exclusive OR circuit U, respectively), and !211 is connected to the Q output of the D flip-flop C1 field. This is the dividing ratio setting port for setting the count number (dividing ratio) of the counter (l) based on the D flip 70 tube u9tJ.
The selection control circuit that controls the selection state of the selection circuit α4 based on the output signal from the frequency division ratio setting circuit υ and the frequency divider uS, and the selection control circuit 4 that controls the selection state 11J at the D terminal. It is a D flip-flop to which the control # signal from M4 is supplied and the output of frequency division a (151) is supplied to the CK terminal.

Figure 2 shows the dividing ratio setting path Ω and the selection I! lII# This is a diagram showing an example of a specific configuration of circuit 4, where f241 is a setting part that determines the frequency division ratio t8 based on the Q output of D flip-flop α (a).%4 is supplied by the small output of setting part 3. Sanne Masabu.

4 is the output power of the frequency-divided au 51; the control unit that is supplied, the OR gate that uses the N-1 output and N+1 output from the setting unit 241 as two-man power, (to) the minute ++! 66 (151 A delay section that delays the rise and fall of the output for a predetermined period of time, the problem is the or game 17
] is output to D141, and the output of the delay section (to) is output to C.
D flip-flops each supplied to the K terminal, output is 07
IJ is a D clip-flop whose output from the AND gate is supplied to the CK terminal.

Next, the IF1 operation will be explained with reference to FIG.

By the way, in FIG. 1, the n9 edges taken out by the D clip-flop (15) and the exclusive OR circuit u8 are connected to the D flip-flop (2) and CK11 as in the conventional case.
Latch the output of the frequency divider α4 and the Q output of the D clip-flop (19), respectively.
is provided to the dividing ratio setting port. Division ratio setting port 12
'', frequency division ratio information is output based on the Q output of the D flip-flop 04. That is.

When both of the Q outputs are at the H level, it is determined that the phase of the reproduction clock is leading, and when both of the Q outputs are at the L level, it is determined that the phase is delayed.

Furthermore, when it is other than n, it is determined that the phases match.

10,000, 1 quasi-signal generating circuit α'' positive phase output [Fig. 5 (see slope)] is the counter U''JK, M9 negative phase output [Fig.
The overflow signals from the large counter circle (131) are as shown in FIG. 3(C) and FIG. Count number of counter ttaαJ (frequency division ratio) multiplied by 3.4
．． It is assumed that one of the three values of 5 is selected.

When the above-mentioned overflow signal is selected by the selection circuit t141 and this selected ratio signal is divided by the frequency divider (15+), the output becomes as shown in FIG. 5(e).

Here, during the L level period of the regenerated clock [Fig. 3 (e)], the count number of counter u3 (13) is fixed at t-4VC, and the selection circuit I selects all the signals that are the same as the previously selected n ratio signal. That is, if the selection circuit I selects, for example, the overflow signal from the counter u2! as a pulse to be generated at the falling edge of the regenerated clock, the counter I1 will also be used as a pulse to be generated at the next rising edge of the external clock.
Using the overflow signal from 4 and counter t
The count number of Lau3 is fixed at t4. Thus, the L level period 1', Jll, of the reproduced clock corresponds to four clocks of the output signal from the reference signal generation circuit συ.

Next, we will explain how to set the H level period T of the reproduced clock to 3.5 clocks, 4 clocks/minute, and 4.5 clocks of the output signal from the reference A No. 8 generation circuit [11J]. do.

First, when setting the H level period t of the reproduced clock to 55 clocks of the 1st signal from the reference signal generation circuit MulJ, the output of the frequency divider u9 is set as shown by arrow A or B in FIG. The selection circuit I selects an overflow signal opposite to the counter signal used to generate the rising edge t or overflow No. 18 of (13) to generate the falling edge of the 1 frequency divider αS output.Further details Then, if the overflow signal of the counter (13) is selected by the selection circuit [41] to create the rising edge of the frequency divider αS output, then vc is
Let the count number t4 be the increase in force by nine tanta uatt. On the other hand, if the selection circuit I selects the over 7 signal of the counter u4 at the ninth rising edge kfli, the count number of the counter α4 is set to 't5.

Next, when setting 45 clocks of the output signal from the reference signal generation circuit ulJ during the H level period of the reproduced clock, it is used to create all the rising and falling edges of the 1 frequency divider 15 output. The overflow signal opposite to the overflow signal may be sent to the selector n in the selection circuit I.

To create the rising edge of the output of the frequency divider.

When using the overflow signal of counter u4,
The count number of counter uau;i is set to fe4, and the counter (1
If using an overflow signal of 3, the counter (
The count number of 14u3 is assumed to be t-5.

Furthermore, when setting the H level period tE of the reproduced clock to 4 clocks of the output signal from the 1 generation circuit αD, the H level period tE of the reproduced clock is set to 4 clocks of the output signal from the 1 generation circuit αD. It is selected by the selection circuit I with the same overflow signal as the overflow number, and the counter tl'jJ
u3 count number 1! All you need is c4 and n.

The operation of the frequency division ratio setting circuit and selection circuit will be explained in more detail with reference to the second factor.

The phase difference information from D flip-flop (19c!I is both at h level) and the 1 frequency division ratio setting section @ is counter
A signal (Sl) to set the field count number (frequency division ratio) k5
)';r is supplied to the corrector and OR gate (2).

The signal supplied to the D flip-flop (2) is supplied to the D4 child of the D flip-flop (2) via the OR gate @.
The D flip-flop 4 outputs the OR gate surface output 7 as the output t clock input of the delay section (to) which delays the rising edge t of the output of the frequency divider αS by a predetermined period of time t. Nine, the Q9s child output of this D flip flow rough is the untobe aai
is applied to the AND gate (1) along with the force.

Therefore, depending on the H level output from the D flip-flop c+IJu and the M-AND gate (2), the Q terminal output is inverted and the selection state of the 1 selection circuit u4 is changed. That is, if the overflow signal of the counter u4 is not selected, the state is changed to select the overflow signal of the counter flat based on the inversion of the Q output of the D flip-flop 6D.

In addition, the control signal to the selection circuit I is transmitted through a 1 frequency divider (151
When the output rises, it is applied to the D flip-flop and is supplied to the correction section. The correction section corrects the frequency division ratio information (number of counts) supplied to the counter α'IJαJ based on the (output) of the latte output CjlIJ, %D flip 70 (c). That is, the 1 selection circuit I
is the overflow signal ti! of counter u4. If the state is set to select one, the count number (dividing ratio) is 1t.
4, the ratio selection circuit I uses a counter (if the overflow signal of 13 is set to be selected seven times), the IC frequency division ratio)? ! -5 and counter n”1Ju
supply l.

Also, the count number of the counter u4μJ during the L level period of the output of the frequency divider αS of t1 (to fix the frequency division ratio to 14, the control section (to) is driven based on the rise of the 1 frequency division 6 output, and At the timing of , the count number (frequency division ratio) 3 information and 7 are set in the correction unit δ.

41 When the phase difference information from the K L and D flip-flops α94 are both at L level, the selection circuit I selects the overflow signal of the counter (131).
& constant n, the count number (divider ratio) is set to t-4, and if the ratio selection circuit I is set to select the overflow signal of the counter (121), the count number (divider ratio) is The frequency ratio] is corrected to t5 and supplied to the counter aaa31.

Ma7tj, live in D flip-flop! If the phase difference information from J12I is at L level or L level or H level, the signal from the 1 frequency division ratio setting section (2) is supplied only to the correction section j, and the counter circle Il dark. is the count number (
A frequency division ratio of 4 is provided. At this time, the selection circuit 1i
41, the same selection state is continued◇ (G) Effect of the invention According to the present invention, the reference signal generating means and the output signal #11 from this reference signal generating means are The variable frequency dividing means of rotating I81 and the first output signal have a phase of 180°J!
a second variable frequency dividing means for frequency dividing the output signal ln2, a selection means for selecting one of the output signals 1 from this Ml and the second variable frequency dividing means, and a signal t'L7 selected by the selection means and a phase comparison means for comparing the phases of the signal and the input signal; Since there is a gap between the dividing ratio setting means for setting and the selection control means for controlling the 1δ selection state of the selection means based on at least one signal from this dividing ratio setting means, the standard gold call signal is generated. The frequency 'a' of the reference signal from the means can be lowered. Therefore, even when regenerating a synchronized clock with little jitter from high-speed received data, it is not necessary to use a high-frequency reference signal generation means as in the past (although it is certainly possible to achieve lock regeneration). I can do it.

[Brief explanation of drawings]

Chestnut Figure 1 is a diagram showing an embodiment of the present invention, and Figure 2 is a division ratio setting circuit and selection 1! The figure which shows an example of II control circuit. FIG. 3 is a diagram showing waveforms at various parts in FIG. 1, FIG. 4 is a diagram showing a conventional example, and FIG. 5 is a diagram showing waveforms at various parts in FIG. (1υ...Reference signal generation circuit, 4u3...Counter (variable frequency dividing means), α4...Selection circuit, αyu■...
D flip-flop consisting of phase comparison means, SiV...
・Dividing ratio setting circuit, ■...Selection 1tllJ@1 circuit. Kuratsugu Nishino (1 other person), Patent Attorney for Ideune Sanyoden A Co., Ltd. ``0 工J IJDGJ 啼-ku --111- Utsumi

Claims (3)

[Claims] (1) a reference signal generating means, a first variable frequency dividing means for frequency dividing one output signal from the reference signal generating means, and a second output signal having a phase different from the first output signal by 180°. a second variable frequency division means for dividing the frequency of the signal, a selection means for selecting the output from the first and second variable frequency division means, and a phase difference between the signal selected by the selection means and the input signal. A phase comparison means for comparison, a frequency division ratio setting means for setting the frequency division ratio of the first and second variable frequency division means according to at least the result of the phase comparison in this phase comparison means, and at least this frequency division ratio setting means. A clock regeneration circuit comprising selection control means for controlling a signal selection state of the selection means based on a signal from the selection means. (2) The frequency division ratio setting means sets the frequency division ratio based on the phase difference information from the phase comparison means, the control signal from the selection control means, and the state of the signal selected by the selection means. A clock recovery circuit according to claim (1). (3) Clock regeneration according to claim (1), wherein the selection control means outputs the selection control signal based on the state of the signal selected by the frequency division ratio setting means and the selection means. circuit.