KR0136048B1 - Synchronization signal detecting system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting a synchronization signal in serial high bit stream data, and a conventional synchronization detector detects a synchronization signal from a data stream and generates data by generating an error of the synchronization signal when different synchronization signals are input. There is a problem that can not output a stable synchronization signal because there is a case that occurs.

Therefore, in order to solve such a conventional problem, the present invention simultaneously detects different synchronization signals transmitted from satellite broadcasts in Europe and determines whether there is an error, and detects a stable synchronization signal and compensates for an error. The synchronization signal detection device is output.

Description

Synchronous Signal Detection Device

1 is a block diagram of a conventional synchronization signal detection apparatus.

2A to 2D are signal timing diagrams of respective parts of a conventional synchronization signal detection apparatus.

3 is a block diagram of a synchronization signal detecting apparatus of the present invention.

4 is a flow chart showing a synchronization signal detection method of the present invention.

(A)-(h) of FIG. 5 are signal timing diagrams of respective parts when the synchronization signal stream is normal in the synchronization signal detection apparatus of the present invention.

(A)-(l) of FIG. 6 are signal timing diagrams of respective parts when the error synchronization signal is the first in the synchronization signal detection apparatus of the present invention.

(A)-(m) of FIG. 7 are signal timing diagrams of respective parts when the error synchronization signal is in a window in the synchronization signal detecting apparatus of the present invention.

* Description of the symbols for the main parts of the drawings *

10: synchronous signal comparison unit 11: synchronous signal detection unit

12: first synchronous signal error detection unit 13: second synchronous signal error detection unit

14: OR gate 15: data conversion unit

16: 1st synchronous signal comparator 17: 2nd synchronous signal comparator

18: first synchronous signal detector 19: window counter

20: third synchronous signal comparator 21: second synchronous signal detector

22: synchronous signal counter 23; synchronous signal converter

24: fourth synchronous signal comparator 25: third synchronous signal detector

26: first synchronous signal error detector 27: first synchronous signal error counter

28: second synchronous signal error detector 29: second synchronous signal error counter

30: synchronous signal pulse detector 31: synchronous signal pulse counter

32: Serial to Parallel Converters 33: Data Latches

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting synchronization signals in serial high bit stream data. In particular, when a drop out occurs, different synchronization signals transmitted by European satellite broadcasting are detected to determine whether there is an error. It detects a stable synchronization signal and compensates for an error and outputs a stable synchronization signal.

The configuration and operation of the conventional synchronization signal detection apparatus will be described below.

First, as shown in FIG. 1, the conventional synchronous detector has a primary detection of a synchronous signal from the synchronous comparison unit 1 for comparing the synchronization of input data with the data output from the synchronous comparison unit 1; The first synchronous detector 2, the window comparator 3 for comparing the synchronous data in the synchronous data section output from the first synchronous detector 2, and the window comparator window in the window comparator 3 A window counter 4 for providing a pulse, a second synchronous detector 5 for secondly detecting a synchronous signal from a signal output from the window comparator 3, and a second synchronous detector 5 A synchronous latch unit 6 for receiving the received synchronous signal and outputting a stable pulse, a serial / parallel converter 7 for converting the input serial data into parallel data, and the serial / parallel converter 7 Data stream by latching the parallel data It is composed of a data latch (8) for outputting.

The operation of the conventional synchronous detector configured as described above will be described below.

First, when data is input to the sync comparator 1 in units of n bytes as shown in FIG. 2A, the sync comparator 1 compares the data and applies it to the first sync detector 2.

At this time, when the first synchronization detector 2 detects a synchronization signal included in the input data as shown in FIG. 2 (b) and applies it to the window counter unit 4, the window counter unit 4 performs a primary By applying the pulse signal to the window comparator 3 as shown in (c) of FIG. 2 by the detected sync signal, the window comparator 3 causes the window and the sync signal detected by the first synchronous detector 2 to The pulse signal output from the counter section 4 is compared and input to the second synchronous detection section 5.

Accordingly, the second synchronous detection unit 5 detects the synchronous signal as shown in (d) of FIG. 2 from the signal output from the window comparator 3 and applies it to the synchronous latch unit 6, thereby providing the synchronous latch unit 6. ) Stably outputs the input synchronization signal.

Meanwhile, the serial / parallel converter 7 converts the input serial data into parallel data and outputs a data stream through the data latch 8.

However, the conventional sync detector detects a sync signal from a data stream, and when a different sync signal is input, an error of the data may occur due to an error of the sync signal. Therefore, there is a problem in that a stable sync signal cannot be output.

Therefore, in order to solve such a conventional problem, the present invention simultaneously detects different synchronization signals transmitted from European satellite broadcasting and determines whether there is an error, accurately detects the synchronization signal, and compensates for an error, thereby outputting a stable synchronization signal. It was made.

The configuration and operation of the synchronization signal detecting apparatus of the present invention for achieving the above object will be described below.

First, the configuration of the synchronization signal detector of the present invention as shown in FIG. 3 is as follows.

A synchronization signal comparison unit 10 for comparing the synchronization signal of the input data, a synchronization signal detection unit 11 for detecting the synchronization signal from the synchronization signal output from the synchronization signal comparison unit 10, and the synchronization signal comparison unit A first synchronous signal error detector 12 for detecting an error of the synchronous signal data output from 10, and a second synchronous signal error detector for detecting an error of the synchronous signal data output from the synchronous signal detector 11; 13) OR gates 14 for resetting the error signals detected by the first and second synchronous signal error detectors 12 and 13 to the synchronous signal comparator 10, and the inputs. And a data converter 15 for converting the synchronization signal of the data to be converted.

The synchronization signal comparator 10 may include first and second synchronization signal comparators 16 and 17 for comparing different synchronization signals of input data, respectively, and the first and second synchronization signal comparators 16. A first synchronous signal detector 18 for detecting and simultaneously detecting a simultaneous signal from the second synchronous signal (17), and a window counter (19) for generating window pulses using the synchronous signal data separated and output from the first synchronous signal detector (18). And a third synchronous signal comparator 20 for comparing the synchronous signal output from the first synchronous signal detector 18 with the synchronous signal output from the window counter 19. 11 is a second synchronous signal detector 21 for separating and detecting the synchronous signal output from the third synchronous signal comparator 20 of the synchronous signal comparator 10, and separated from the second synchronous signal detector 21. Counter at regular intervals using the output synchronization signal And a synchronization signal converter 23 for converting the synchronization signal counter 22 and the synchronization signal output from the second synchronization signal detector 21 into a byte signal when the output signal is a bit signal. A fourth synchronous signal comparator 24 for comparing the synchronous signal output from the signal converter 23 with the synchronous signal output from the synchronous signal counter 22, and a synchronous output compared with the fourth synchronous signal comparator 24 and outputted; The third synchronization signal detector 25 detects a synchronization signal when there is no error in the signal.

In addition, the first synchronous signal error detector 12 may include a first synchronous signal error detector 26 and a first synchronous signal error counter 27 for resetting when the synchronous signal data is an error in the input data stream. The second synchronous signal error detector 13 includes a second synchronous signal error detector 28 for detecting a synchronous signal error when an error occurs in the synchronous signal output from the fourth synchronous signal comparator 24, and A second synchronization signal error counter 29 for detecting the number of errors generated by the second synchronization signal error detector 28 and outputted from the synchronization signal counter 22 of the synchronization signal extracting unit 11; A synchronous signal pulse detector 30 and a synchronous signal pulse counter 31 which reset the second synchronous signal error detection 28 within a predetermined period by using the signal.

The data converter 15 latches a serial / parallel converter 32 for converting input data into parallel data and a data latch for latching parallel data output from the serial / parallel converter 32 to output a data stream. It consists of (33).

4 shows the detection of the synchronization signal with reference to the synchronization signal detection device of FIG. 3 in the synchronization signal detection method.

The operation and effect of the synchronization signal detecting apparatus of the present invention configured as described above will be described sequentially with reference to FIGS. 3 and 4 when the synchronization signal is normal, first reappearance, and in the window.

First, when the synchronization signal detecting apparatus is normal, it is as follows.

As shown in (a) of FIG. 5, different synchronization signals of input data are constantly transmitted through the first and second synchronization signal comparators 16 and 17 of the synchronization signal comparator 10, with n bytes, without errors. While detecting the pulse signal as shown in (b) and (c) of FIG. 5, and the detected pulse signal is detected by the first synchronous signal detector 18 and as shown in (b) and (c) of FIG. The synchronizing signal shown in FIG. 5 (d) in which the signals are combined is detected.

In addition, the window counter 19 counters the synchronization signal for a predetermined period (e.g., set to 180 when N = 240) based on the synchronization signal detected by the first synchronization signal detector 18. A window pulse signal as shown in e) is generated.

At this time, the third synchronous signal comparator 20 generates the pulse signal of (d) of FIG. 5 and the window pulse signal of (e) of FIG.

At this time, the third synchronous signal comparator 20 compares the pulse signal of (d) of FIG. 5 with the window pulse of (e) of FIG. 5 while inputting the second synchronous signal comparator 17 of FIG. Outputs a pulse signal and inputs it to the second detector 21 of the synchronization signal detection unit 11, and the window counter 19 (f) of FIG. The pulse signal is generated as shown in (g) of FIG. 5 through the synchronization signal counter 22 of the synchronization signal detection unit 11 at a predetermined interval (for example, N = 204) based on the pulse signal of FIG.

In addition, the fourth synchronous signal comparator 24 compares the detected pulse signals of (f) and (g) of FIG. 5 with the detected third synchronous signal detector (3). 25, a synchronization signal is detected as shown in FIG. 5 (h), and the synchronization signal converter 23 of the synchronization signal detection unit 11 is a block diagram for converting a bit signal of the synchronization signal into a byte signal. to be.

On the other hand, when the error synchronization signal is the first as shown in FIG. 6, when the same data as the synchronization signal exists in the data which is not the synchronization signal as shown in FIG. Since the data is not a synchronization signal, an error must be generated to detect the next synchronization signal.

That is, when a data stream of n data bytes as shown in (a) of FIG. 6 is input, the first sync signal detector 18 of the sync signal comparison unit 10 receives the sync signal pulse as shown in (b) of FIG. If the first input pulse is an error synchronization signal, the window counter 19 outputs a pulse as shown in FIG. 6C based on the error synchronization signal as shown in FIG.

In the second synchronous signal detector 21 of the synchronous signal detector 11, the synchronous signal is not detected, and through the third synchronous signal comparator 20 of the synchronous signal comparator 10, (b) of FIG. 6 and ( By comparing the pulse signal of c) and detecting the error synchronization signal as shown in (d) of FIG. 6 through the first synchronization signal error detector 26 of the first synchronization signal error detection unit 12, the detected error synchronization When the signal is repeatedly counted through the first synchronization signal error counter 27, the pulse signal as shown in (e) of FIG. 6 is output, and the synchronization signal comparison unit 10 outputs the reset pulse signal of (f) in FIG. Resetting the synchronization signal counter 22 of the synchronization signal detection unit 11 while resetting the window counter 19 of FIG. 9 through the OR gate 14 causes a new data stream to be received as shown in FIG. .

At this time, when the data stream is normal as shown in (g) of FIG. 6, the first synchronization signal detector 18 detects a synchronization signal as shown in (e) of FIG. 6, and based on the detected synchronization signal Thus, the window counter 19 generates the window pulse signal as shown in FIG. 6 (f) while counting the synchronization signal at a predetermined interval.

The third synchronous signal comparator 20 compares the pulse signal of (e) of FIG. 6 with the window pulse signal of (i) of FIG. 6, and is input to the second synchronous signal comparator 17. As shown in (j) of FIG. 1, a pulse signal is output and input to the second synchronous signal detector 21 of the synchronous signal detector 11. The window counter 19 is a diagram for checking whether a synchronous signal is periodically input within a section. A pulse signal is generated as shown in (k) of FIG. 6 through the synchronization signal counter 22 of the synchronization signal detector 11 at a predetermined interval based on the pulse signal of FIG. 6 (j).

In addition, the fourth synchronous signal comparator 24 compares the detected pulse signals of (j) and (k) of FIG. 6 to convert the synchronous signal inputted to the first synchronous signal comparator 16 into a third synchronous signal detector ( Through 25), the synchronization signal is detected as shown in (l) of FIG.

FIG. 7 shows a case where an error synchronization signal is in a window. When a data stream as shown in FIG. 7A is input, the first synchronization signal detector 18 of the synchronization signal comparison unit 10 A synchronization signal as shown in FIG. 7B is detected.

At this time, the window counter 19 outputs the window pulse as shown in (c) of FIG. 7 based on the first pulse among the synchronization signals of FIG. When the error signal is mixed in the window pulse as shown in c), the pulse shown in (d) of FIG. 7 is output through the second synchronization signal detector 21 of the synchronization signal detector 11.

In addition, the pulse signal as shown in (e) of FIG. 7 is output through the synchronous signal counter 22 while the pulse signal as shown in (d) of FIG. 7 is output through the fourth synchronous signal comparator 24. Comparing the pulse signal of (d) and (e) of FIG. 7 and outputting an error signal, at this time, the second synchronous signal error detector 28 and the second synchronous signal error counter of the second synchronous signal error detector 13 29, the pulse signal is output as shown in FIG. 7 (f).

Further, if the first synchronous signal error counter 29 repeatedly counts the signal pulses as shown in (f) of FIG. 7, the synchronous signal comparator (7) outputs the reset pulse signal of (g) of FIG. When the window counter 19 of FIG. 10 is reset through the OR gate 14 and the sync signal counter 22 of the sync signal detection unit 11 is reset, a data stream as shown in FIG. 7 (h) is newly received. do.

Then, the synchronization signal pulse detector 30 and the synchronization signal pulse counter 31 of the second synchronization signal error detector 13 return the second synchronization signal error detector 28 at regular intervals when the synchronization error does not continue. It is set.

On the other hand, when the data stream is normal as shown in (h) of FIG. 7, the first synchronous signal detector 18 detects a synchronous signal as shown in (i) of FIG. 7 and based on the detected sync signal. Thus, the window counter 19 generates a window pulse signal as shown in FIG. 7 (j) while counting the synchronization signal at a predetermined interval.

In addition, the third synchronous signal comparator 20 inputs the second synchronous signal comparator 17 while comparing the pulse signal of (i) of FIG. 7 with the window pulse signal of (j) of FIG. A pulse signal as shown in (k) is output and input to the second synchronous signal detector 21 of the synchronous signal detector 11. The window counter 19 is a diagram for checking whether a synchronous signal is periodically input within a section. A pulse signal as shown in (l) of FIG. 7 is generated through the synchronization signal counter 22 of the synchronization signal detector 11 at a predetermined interval based on the pulse signal of FIG. 7 (k).

In addition, the fourth synchronous signal comparator 24 compares the detected pulse signals of (k) and (l) of FIG. 7 to convert the synchronous signal inputted to the first synchronous signal comparator 16 into a third synchronous signal detector ( 25), a synchronization signal as shown in FIG. 7 (m) is detected and output. On the other hand, the input data is converted into parallel data by the serial / parallel converter 32 of the data converter 15, and then data latched. It is output through (33).

As described above, the present invention has the effect of simultaneously detecting different synchronization signals transmitted in the European satellite broadcasting and detecting whether there is an error while detecting a stable synchronization signal and compensating for the occurrence of an error to output a stable synchronization signal. .

Claims (3)

A synchronization signal comparison unit 10 for comparing the synchronization signal of the input data, a synchronization signal detection unit 11 for detecting the synchronization signal from the synchronization signal output from the synchronization signal comparison unit 10, and the synchronization signal comparison unit A first synchronous signal error detector 12 for detecting an error of the synchronous signal data output from 10, and a second synchronous signal error detector for detecting an error of the synchronous signal data output from the synchronous signal detector 11; 13) OR gates 14 for resetting the error signals detected by the first and second synchronous signal error detectors 12 and 13 to the synchronous signal comparator 10, and the inputs. A synchronization signal detection device comprising a data converter (15) for converting a synchronization signal of data to be converted. 2. The synchronization signal comparator 10 of claim 1, wherein the synchronization signal comparator 10 includes first and second synchronization signal comparators 16 and 17 for comparing different synchronization signals of input data, respectively, and the first and second synchronization signals. A window for generating window pulses using the first synchronous signal detector 18 which detects the synchronous signal from the comparators 16 and 17 and the synchronous signal data separated and output from the first synchronous signal detector 18. And a third synchronization signal comparator 20 for comparing the synchronization signal output from the window counter 19 with the counter 19 and the synchronization signal output from the first synchronization signal detector 18. The signal detector 11 includes a second synchronous signal detector 21 for separating and detecting a synchronous signal output from the third synchronous signal comparator 20 of the synchronous signal comparator 10, and the second synchronous signal detector 21. Car at regular intervals using the synchronization signal And a synchronization signal converter 23 for converting the synchronization signal counter 22 and the synchronization signal output from the second synchronization signal detector 21 into a byte signal when the output signal is a bit signal. The fourth synchronous signal comparator 24 comparing the synchronous signal output from the synchronous signal converter 23 and the synchronous signal output from the synchronous signal counter 22 and the fourth synchronous signal comparator 24 are compared and output. And a third synchronous signal detector (25) for detecting the synchronous signal when there is no error in the synchronous signal. 2. The first synchronous signal error detector (12) according to claim 1, wherein the first synchronous signal error detector (12) is configured to reset the first synchronous signal error detector (26) and the first synchronous signal error counter to reset when the synchronous signal data is an error in the input data stream. And a second synchronous signal error detector 13 for detecting a synchronous signal error when an error occurs among the synchronous signals output from the fourth synchronous signal comparator 24. ), A second synchronous signal error counter 29 for detecting the number of errors generated and output by the second synchronous signal error detector 28, and a synchronous signal counter 22 of the synchronous signal detector 11 And a synchronizing signal pulse detector (30) and a synchronizing signal pulse counter (31) for resetting the second synchronizing signal error detector (28) within a predetermined period by using the output synchronizing signal.