JPS6428039U - - Google Patents
Info
- Publication number
- JPS6428039U JPS6428039U JP12257187U JP12257187U JPS6428039U JP S6428039 U JPS6428039 U JP S6428039U JP 12257187 U JP12257187 U JP 12257187U JP 12257187 U JP12257187 U JP 12257187U JP S6428039 U JPS6428039 U JP S6428039U
- Authority
- JP
- Japan
- Prior art keywords
- value
- received signal
- register
- aforementioned
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例の構成図、第２図は
本考案の一実施例のタイミングチヤート、第３図
本考案の一実施例のフローチヤートである。
１…マイクロコンピユータ、２…クロツク発生
回路、３…ＲＡＭ、４…ＲＯＭ、５…シフトレジ
スタ、ＦＲＣ…フリーランニングカウンタ、ＯＣ
Ｒ…アウトプツトコンベアレジスタ、ＩＣＲ…イ
ンプツトキヤプチエアレジスタ。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart of an embodiment of the present invention, and FIG. 3 is a flowchart of an embodiment of the present invention. 1... Microcomputer, 2... Clock generation circuit, 3... RAM, 4... ROM, 5... Shift register, FRC... Free running counter, OC
R...Output conveyor register, ICR...Input capture air register.
Claims (1)
ツク発振器からなるマイクロコンピユータ回路と
前述のクロツク発振器のクロツクを計数するカウ
ンタと、前述のカウンタとの値を比較するレジス
タと、入力信号が変化たときに前述のカウンタの
値を覚えておくレジスタと、受信信号を入力する
シフトレジスタからなる回路において、受信信号
が変化したときから、前述のクロツクの所定カウ
ント毎に受信信号をシフトレジスタに入れ、スト
ツプビツトがあるときシフトレジスタの値を受信
バツフアに移すことを特徴とする直列信号受信装
置。 A microcomputer circuit consisting of a microcomputer, ROM, RAM, and a clock oscillator; a counter that counts the clocks of the aforementioned clock oscillator; a register that compares the value with the aforementioned counter; In a circuit consisting of a register that remembers a value and a shift register that inputs the received signal, the received signal is input into the shift register at every predetermined count of the aforementioned clocks from when the received signal changes, and when there is a stop bit, the shift register is input. A serial signal receiving device characterized in that the value of is transferred to a receiving buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12257187U JPS6428039U (en) | 1987-08-12 | 1987-08-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12257187U JPS6428039U (en) | 1987-08-12 | 1987-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6428039U true JPS6428039U (en) | 1989-02-17 |
Family
ID=31370625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12257187U Pending JPS6428039U (en) | 1987-08-12 | 1987-08-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6428039U (en) |
-
1987
- 1987-08-12 JP JP12257187U patent/JPS6428039U/ja active Pending
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