JPH033054U

JPH033054U -

Info

Publication number: JPH033054U
Application number: JP6321089U
Authority: JP
Priority date: 1989-06-01
Filing date: 1989-06-01
Publication date: 1991-01-14

Description

[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク図、第２
図は共有バス方式のシステム図、第３図ａ、第３
図ｂは実施例のタイミングチヤート、第４図は実
施例の状態遷移図、第５図は実施例のフローチヤ
ートである。１……バスリクエスト発生回路、２……論理回
路、３……要求調停回路、４……優先順位決定回
路、８……ペンデイングリクエスト帰還回路。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a system diagram of the shared bus system, Figure 3a, Figure 3
FIG. b is a timing chart of the embodiment, FIG. 4 is a state transition diagram of the embodiment, and FIG. 5 is a flow chart of the embodiment. 1...Bus request generation circuit, 2...Logic circuit, 3...Request arbitration circuit, 4...Priority determination circuit, 8...Pending request feedback circuit.

Claims

[Claim for Utility Model Registration] In a shared bus arbitration system that arbitrates requests for shared bus use from multiple microprocessors, a bus request generation circuit that outputs a bus request signal for each microprocessor; A circuit that logically ANDs the processor's bus request signal and the negation of the bus grant signal for the microprocessor and outputs it as a pending bus request signal using an open collector type driver, and a cloth on the bus that wire-ORs this output. and request arbitration for outputting a bus grant signal that allows the microprocessor whose bus request signal is set to "1" to continue acquiring the right to use the bus when the pending request signal from each of the microprocessors is "0". and a pending request feedback circuit that inputs an AND of the bus request signal of each microprocessor and the negation of the bus grant signal for the microprocessor to the bus request generation circuit. A shared bus arbitration system.