JPS62147046U - - Google Patents
Info
- Publication number
- JPS62147046U JPS62147046U JP3434186U JP3434186U JPS62147046U JP S62147046 U JPS62147046 U JP S62147046U JP 3434186 U JP3434186 U JP 3434186U JP 3434186 U JP3434186 U JP 3434186U JP S62147046 U JPS62147046 U JP S62147046U
- Authority
- JP
- Japan
- Prior art keywords
- arbiter
- performs
- unit
- gate
- bus arbitration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011144 upstream manufacturing Methods 0.000 claims 5
- 230000010365 information processing Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Hardware Redundancy (AREA)
- Bus Control (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は従来装置の説明図である。
１０…並列バス、２０，３０，４０…ユニツト
、２１，３１，４１…アービタ、２２，３２，４
２…第１のゲート、２３，３３，４３…第２のゲ
ート。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional device. 10... Parallel bus, 20, 30, 40... Unit, 21, 31, 41... Arbiter, 22, 32, 4
2...first gate, 23, 33, 43...second gate.
Claims (1)
複数のユニツトが結合された情報処理装置であつ
て、 各ユニツトは、当該並列バスのバスアービトレ
ーシヨンを行うアービタ、当該アービタの入力信
号と出力信号との論理演算を行い下流側に出力す
る第１のゲート、上流側の隣接ユニツト及びこれ
の上流側の隣接ユニツトの出力信号の論理演算を
行い前記アービタに入力する第２のゲートを有し
、 第１のゲートは当該ユニツトを含む上流側のユ
ニツトにバスアービトレーシヨンを行う権利を有
するアービタが存在するか否か報知し、 第２のゲートは上流側のユニツトに権利を有す
るアービタのないときは当該アービタに権利を付
与し、上流側のユニツトに権利を有するアービタ
のあるときは当該アービタに権利を与えないよう
にした ことを特徴とする情報処理装置。[Claims for Utility Model Registration] An information processing device in which a plurality of units are connected by a parallel bus that performs bus arbitration, and each unit includes an arbiter that performs bus arbitration of the parallel bus, and an arbiter that performs bus arbitration of the parallel bus. A first gate that performs a logical operation on an input signal and an output signal and outputs it to the downstream side, a second gate that performs a logical operation on the output signal of an adjacent unit on the upstream side, and an output signal of an adjacent unit on the upstream side thereof and inputs it to the arbiter. The first gate notifies the upstream unit including the unit whether there is an arbiter that has the right to perform bus arbitration, and the second gate notifies the upstream unit that has the right to perform bus arbitration. An information processing device characterized in that when there is no arbiter that has the right, the right is granted to the arbiter, and when there is an arbiter that has the right in an upstream unit, the right is not granted to the arbiter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3434186U JPS62147046U (en) | 1986-03-10 | 1986-03-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3434186U JPS62147046U (en) | 1986-03-10 | 1986-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147046U true JPS62147046U (en) | 1987-09-17 |
Family
ID=30842796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3434186U Pending JPS62147046U (en) | 1986-03-10 | 1986-03-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147046U (en) |
-
1986
- 1986-03-10 JP JP3434186U patent/JPS62147046U/ja active Pending
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