JPH03127907U - - Google Patents
Info
- Publication number
- JPH03127907U JPH03127907U JP3676990U JP3676990U JPH03127907U JP H03127907 U JPH03127907 U JP H03127907U JP 3676990 U JP3676990 U JP 3676990U JP 3676990 U JP3676990 U JP 3676990U JP H03127907 U JPH03127907 U JP H03127907U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- processors
- bus
- slaves
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Numerical Control (AREA)
Description
第１図はこの考案の一実施例による２個のプロ
セツサとバスの構成を示す構成図、第２図は従来
の２個のプロセツサとバスの構成を示す構成図で
ある。
図において、１はシングルバスマスタバスＡ、
２はバスマスタ１、３はバススレーブ、４はシン
グルバスマスタバスＢ、５はバスタマス２である
。なお、図中、同一符号同一、または相当部分を
示す。
FIG. 1 is a block diagram showing the structure of two processors and a bus according to an embodiment of this invention, and FIG. 2 is a block diagram showing the structure of two conventional processors and a bus. In the figure, 1 is a single bus master bus A;
2 is a bus master 1, 3 is a bus slave, 4 is a single bus master bus B, and 5 is a bus master 2. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
それぞれのプロセツサはそれぞれのバスを有し、
該バスは該プロセツサと１対１に対応し、かつ該
プロセツサが総括するバスに他のプロセツサがス
レーブとして配置され、スレーブとして配置され
たプロセツサはマスタとして配置された該プロセ
ツサによつて総括され、かつ１対１で対応するバ
スを有し、該プロセツタと該プロセツサのスレー
ブとして配置されたプロセツサがそれぞれ管理す
るバスが互いに互換性を有し、各プロセツサが各
バスを介して階層的に配置することを特徴とする
ロボツトの制御装置。 In systems with multiple processors,
Each processor has its own bus,
The bus has a one-to-one correspondence with the processor, and other processors are arranged as slaves on the bus controlled by the processor, and the processors arranged as slaves are controlled by the processor arranged as a master, The processor has buses that correspond one-to-one, and the buses managed by the processor and the processors arranged as slaves of the processor are compatible with each other, and the processors are arranged hierarchically via each bus. A robot control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3676990U JPH03127907U (en) | 1990-04-05 | 1990-04-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3676990U JPH03127907U (en) | 1990-04-05 | 1990-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03127907U true JPH03127907U (en) | 1991-12-24 |
Family
ID=31543294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3676990U Pending JPH03127907U (en) | 1990-04-05 | 1990-04-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03127907U (en) |
-
1990
- 1990-04-05 JP JP3676990U patent/JPH03127907U/ja active Pending