JPS62183257U - - Google Patents
Info
- Publication number
- JPS62183257U JPS62183257U JP7081786U JP7081786U JPS62183257U JP S62183257 U JPS62183257 U JP S62183257U JP 7081786 U JP7081786 U JP 7081786U JP 7081786 U JP7081786 U JP 7081786U JP S62183257 U JPS62183257 U JP S62183257U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- coincidence detection
- access request
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Multi Processors (AREA)
Description
第１図はこの考案のアクセス権調停装置の一実
施例を示す電気回路図、第２図はアクセス要求信
号の組合せを示す図、第３図はデユアルポートメ
モリ制御装置を示すブロツク図、第４図は従来例
を示す電気回路図。
５，８，１２，１３……ＡＮＤゲート、６，７
，１０……インバータ、９……ＯＲゲート、１１
……Ｄフリツプフロツプ。
FIG. 1 is an electric circuit diagram showing one embodiment of the access right arbitration device of this invention, FIG. 2 is a diagram showing combinations of access request signals, FIG. 3 is a block diagram showing a dual port memory control device, and FIG. The figure is an electric circuit diagram showing a conventional example. 5, 8, 12, 13...AND gate, 6, 7
, 10... Inverter, 9... OR gate, 11
...D flipflop.
Claims (1)
を検出する一致検出手段と、一致検出手段からの
非一致状態検出信号をクロツク信号とし、かつ一
方のアクセス要求信号をデータ信号とするフリツ
プフロツプと、各アクセス要求信号により開閉さ
れ、フリツプフロツプのＱ出力信号、および出
力信号をそれぞれポート切換信号として出力する
ゲート手段とを具備することを特徴とするデユア
ルポートメモリアクセス権調停装置。 Coincidence detection means for detecting whether a pair of access request signals match; a flip-flop that uses a non-coincidence detection signal from the coincidence detection means as a clock signal and uses one access request signal as a data signal; 1. A dual-port memory access right arbitration device comprising gate means that is opened and closed by each access request signal and outputs a Q output signal of a flip-flop and an output signal as a port switching signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081786U JPS62183257U (en) | 1986-05-12 | 1986-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7081786U JPS62183257U (en) | 1986-05-12 | 1986-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183257U true JPS62183257U (en) | 1987-11-20 |
Family
ID=30912797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7081786U Pending JPS62183257U (en) | 1986-05-12 | 1986-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183257U (en) |
-
1986
- 1986-05-12 JP JP7081786U patent/JPS62183257U/ja active Pending
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