JPS60148648U - Shared memory control circuit in dual processor system - Google Patents
Shared memory control circuit in dual processor systemInfo
- Publication number
- JPS60148648U JPS60148648U JP3735684U JP3735684U JPS60148648U JP S60148648 U JPS60148648 U JP S60148648U JP 3735684 U JP3735684 U JP 3735684U JP 3735684 U JP3735684 U JP 3735684U JP S60148648 U JPS60148648 U JP S60148648U
- Authority
- JP
- Japan
- Prior art keywords
- shared memory
- control circuit
- memory control
- processor system
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例の構成を示す回路図、第２
図は同上回路の動作例を示すタイミングチャートである
。
ＣＰＵ ｌ 、 ＣＰＵ ２・・・・・・プロセッサ、
１０・・・・・・共有メモリ、２０・・・・・・制御回
路、３０・・・・・・切換回 ・路、２１，２２
・・・・・・アドレスデコーダ、３１．３．２・・・・
・・ライチ回路、４１，４２，５１，５２・・・・・・
遅延回路、Ｎ、１．ＡＬ２・・・・・・アドレス確定信
号、［）１．ＩＤ２・・・・・・バスアイドル信号。Figure 1 is a circuit diagram showing the configuration of an embodiment of this invention;
The figure is a timing chart showing an example of the operation of the above circuit. CPU l, CPU 2...processor,
10... Shared memory, 20... Control circuit, 30... Switching circuit, 21, 22
...Address decoder, 31.3.2...
...Lichi circuit, 41, 42, 51, 52...
Delay circuit, N, 1. AL2...address confirmation signal, [)1. ID2...Bus idle signal.
Claims (1)
それぞれ検出してリクエスト信号を発生する２つのアド
レスデコーダと、両アドレスデコーダの出力をそれぞれ
対応する上記プロセッサのアドレス確定信号でラッチし
、かつ対応する上記プロセッサのバスアイドル信号でク
リアされるラッチ回路とを設け、上記リクエスト信号を
早く上記ラッチ回路にラッチした側の上記プロセッサに
一当該ラッチ回路がクリアされるまで上記共有メモリへ
のアクセス権を与えるように構成したことを特徴とする
デュアル・プロセッサ・システムにおける共有メ゛モリ
の制御回鮎。two address decoders each detecting that two processors address the shared memory and generate a request signal; and two address decoders each latching the outputs of both address decoders with the address determination signal of the corresponding processor; A latch circuit that is cleared by a bus idle signal of a processor is provided, and the processor that latches the request signal early in the latch circuit is given access to the shared memory until the latch circuit is cleared. A shared memory control circuit in a dual processor system characterized by being configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3735684U JPS60148648U (en) | 1984-03-15 | 1984-03-15 | Shared memory control circuit in dual processor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3735684U JPS60148648U (en) | 1984-03-15 | 1984-03-15 | Shared memory control circuit in dual processor system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60148648U true JPS60148648U (en) | 1985-10-02 |
Family
ID=30543358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3735684U Pending JPS60148648U (en) | 1984-03-15 | 1984-03-15 | Shared memory control circuit in dual processor system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60148648U (en) |
-
1984
- 1984-03-15 JP JP3735684U patent/JPS60148648U/en active Pending
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