JPS6293249U - - Google Patents
Info
- Publication number
- JPS6293249U JPS6293249U JP18414685U JP18414685U JPS6293249U JP S6293249 U JPS6293249 U JP S6293249U JP 18414685 U JP18414685 U JP 18414685U JP 18414685 U JP18414685 U JP 18414685U JP S6293249 U JPS6293249 U JP S6293249U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- selection signal
- latch means
- control device
- access control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案を実施したメモリ・アクセス制
御装置の回路図、第２図は本考案の実施例による
メモリ・アクセス制御装置の動作を説明するため
のタイム・チヤート、第３図は従来のメモリ・ア
クセス制御装置の例を示す回路図、第４図は第３
図に示した従来のメモリ・アクセス制御装置の動
作を表わすタイムチヤート、第５図は従来のもう
１つのメモリ・アクセス制御装置の例を示す回路
図、第６図は第５図に示した従来のメモリ・アク
セス制御装置の動作を表わすタイム・チヤートで
ある。
１……アドレス・デコーダ、２……第１のラツ
チ手段、２１，２２，２３……Ｄフリツプ・フロ
ツプ回路、３……コンパレータ、４……第２のラ
ツチ手段、５……バス応答制御回路、６……トラ
ンシーバ、ｍ１，ｍ２，ｍ３……メモリ素子、Ｂ
Ａ……アドレス・バス、ＢＤ……データ・バス、
ＢＣ……コントロール・バス、ｄＢ……内部デー
タ・バス。
FIG. 1 is a circuit diagram of a memory access control device embodying the present invention, FIG. 2 is a time chart for explaining the operation of the memory access control device according to an embodiment of the present invention, and FIG. 3 is a conventional memory access control device. A circuit diagram showing an example of a memory access control device, FIG.
A time chart showing the operation of the conventional memory access control device shown in the figure, FIG. 5 is a circuit diagram showing another example of the conventional memory access control device, and FIG. 6 is a conventional memory access control device shown in FIG. 2 is a time chart showing the operation of the memory access control device of FIG. DESCRIPTION OF SYMBOLS 1...Address decoder, 2...First latch means, 21 , 22 , 23 ...D flip-flop circuit, 3...Comparator, 4...Second latch means, 5...Bus Response control circuit, 6...transceiver, m1 , m2 , m3 ...memory element, B
A...address bus, BD...data bus,
BC...Control bus, dB...Internal data bus.
Claims (1)
られるアドレスにより前記メモリ素子へアクセス
を行なうメモリ・アクセス制御装置において、前
記プロセツサから与えられるアドレスをデコード
してメモリ選択信号を出力するアドレス・デコー
ダと、このメモリ選択信号をラツチする第１のラ
ツチ手段と、次のバス・サイクルのはじめに前記
第１のラツチ手段に記憶されたメモリ選択信号と
今回与えられたメモリ選択信号とを比較する比較
手段と、この比較手段の比較結果をラツチする第
２のラツチ手段と、この第２のラツチ手段のラツ
チ出力と前記アドレス・デコーダからの信号とに
よつてバス・サイクルを引き伸ばす応答信号を出
力するバス応答制御回路を有するメモリ・アクセ
ス制御装置。 A memory access control device having a plurality of memory elements and accessing the memory elements using addresses given from a processor includes an address decoder that decodes the address given from the processor and outputs a memory selection signal; a first latch means for latching a memory selection signal; a comparison means for comparing the memory selection signal stored in the first latch means with the currently applied memory selection signal at the beginning of the next bus cycle; a second latch means for latching the comparison result of the comparison means; and a bus response control circuit for outputting a response signal for extending the bus cycle based on the latch output of the second latch means and the signal from the address decoder. A memory access control device having:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18414685U JPS6293249U (en) | 1985-11-29 | 1985-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18414685U JPS6293249U (en) | 1985-11-29 | 1985-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6293249U true JPS6293249U (en) | 1987-06-15 |
Family
ID=31131543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18414685U Pending JPS6293249U (en) | 1985-11-29 | 1985-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6293249U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55129847A (en) * | 1979-03-30 | 1980-10-08 | Panafacom Ltd | Access system of memory unit |
| JPS6140657A (en) * | 1984-08-01 | 1986-02-26 | Yaskawa Electric Mfg Co Ltd | System for accessing low-speed memory in high speed |
-
1985
- 1985-11-29 JP JP18414685U patent/JPS6293249U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55129847A (en) * | 1979-03-30 | 1980-10-08 | Panafacom Ltd | Access system of memory unit |
| JPS6140657A (en) * | 1984-08-01 | 1986-02-26 | Yaskawa Electric Mfg Co Ltd | System for accessing low-speed memory in high speed |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6293249U (en) | ||
| JPH0466648U (en) | ||
| JP2912090B2 (en) | Time slot interchange circuit | |
| JPS6241438Y2 (en) | ||
| JPS61253559A (en) | Microprocessor | |
| JPS629850U (en) | ||
| JPH0245274B2 (en) | ||
| JPH02123640U (en) | ||
| JPS61172325U (en) | ||
| JPS60148648U (en) | Shared memory control circuit in dual processor system | |
| JPS63168549U (en) | ||
| JPH0263146U (en) | ||
| JPS62112750U (en) | ||
| JPS60111598U (en) | memory element | |
| JPS6277659A (en) | Data access controller for memory device | |
| JPS623699U (en) | ||
| JPS63179547U (en) | ||
| JPS6057855U (en) | Dual CPU information processing device | |
| JPS6074297U (en) | RAM access circuit | |
| JPH04299752A (en) | Microprocessor | |
| JPS6271747U (en) | ||
| JPH05174574A (en) | Memory controller | |
| JPS63103151U (en) | ||
| JPS63163541U (en) | ||
| JPS59155639U (en) | memory selection device |