JPS62112750U - - Google Patents
Info
- Publication number
- JPS62112750U JPS62112750U JP20246285U JP20246285U JPS62112750U JP S62112750 U JPS62112750 U JP S62112750U JP 20246285 U JP20246285 U JP 20246285U JP 20246285 U JP20246285 U JP 20246285U JP S62112750 U JPS62112750 U JP S62112750U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- random access
- address
- physical address
- processor section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003068 static effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案のメモリ・アクセス装置を実施
した回路構成ブロツク図、第２図はプロセツサ部
から与えられる論理アドレスとアドレス変換器に
よつて変換された物理アドレスを表わす図である
。
１…プロセツサ部、２…スタテイツク・カラム
ＤＲＡＭ、３…アドレス変換器、４…アドレス・
ラツチ、５…比較器、６…ＲＡＭ制御器、７…入
出力バツフア、８…デコーダ、９…マルチプレク
サ。
FIG. 1 is a block diagram of a circuit configuration implementing the memory access device of the present invention, and FIG. 2 is a diagram showing a logical address given from a processor section and a physical address translated by an address converter. 1... Processor section, 2... Static column DRAM, 3... Address converter, 4... Address converter.
Latch, 5... Comparator, 6... RAM controller, 7... Input/output buffer, 8... Decoder, 9... Multiplexer.
Claims (1)
スが行なわれ、仮想記憶とページ・サイズが同一
なスタテイツク・カラム・ランダム・アクセス・
メモリと、前記プロセツサ部から論理アドレスの
一部が与えられ、前記スタテイツク・カラム・ラ
ンダム・アクセス・メモリに対する物理アドレス
に変換を行なうアドレス変換器と、前回物理アド
レスをラツチするアドレス・ラツチと、前回物理
アドレスと今回物理アドレスとを比較する比較器
と、この比較器から一致出力がなされた際に前記
スタテイツク・カラム・ランダム・アクセス・メ
モリに対して該当データ出力有効信号を出力する
ランダム・アクセス・メモリ制御器とからなるメ
モリ・アクセス装置。 The processor section and the static column random access memory that is accessed from this processor section and have the same virtual memory and page size.
a memory; an address converter to which a portion of the logical address is given from the processor section and converts it into a physical address for the static column random access memory; an address latch that latches the previous physical address; a comparator that compares the physical address with the current physical address; and a random access controller that outputs a corresponding data output valid signal to the static column random access memory when a match is output from the comparator. A memory access device consisting of a memory controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985202462U JPH0441393Y2 (en) | 1985-12-27 | 1985-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985202462U JPH0441393Y2 (en) | 1985-12-27 | 1985-12-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62112750U true JPS62112750U (en) | 1987-07-17 |
| JPH0441393Y2 JPH0441393Y2 (en) | 1992-09-29 |
Family
ID=31166864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985202462U Expired JPH0441393Y2 (en) | 1985-12-27 | 1985-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0441393Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5898893A (en) * | 1981-12-09 | 1983-06-11 | Toshiba Corp | Information processing device |
| JPS5919286A (en) * | 1982-07-23 | 1984-01-31 | Hitachi Ltd | Address converter |
-
1985
- 1985-12-27 JP JP1985202462U patent/JPH0441393Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5898893A (en) * | 1981-12-09 | 1983-06-11 | Toshiba Corp | Information processing device |
| JPS5919286A (en) * | 1982-07-23 | 1984-01-31 | Hitachi Ltd | Address converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0441393Y2 (en) | 1992-09-29 |
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