JPS61172325U - - Google Patents
Info
- Publication number
- JPS61172325U JPS61172325U JP5420685U JP5420685U JPS61172325U JP S61172325 U JPS61172325 U JP S61172325U JP 5420685 U JP5420685 U JP 5420685U JP 5420685 U JP5420685 U JP 5420685U JP S61172325 U JPS61172325 U JP S61172325U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- cpu
- signal
- pulse
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案の一実施例を示すリセツト装置
を含む電子機器装置の概略構成図、第２図は第１
図の動作タイムチヤートである。
１：ＣＰＵ、２：リセツト番地デコーダ、３：
ワンシヨツトパルス発生回路、４：ＯＲ回路、５
：リセツトメモリ、６：アドレスバス、７：リー
ド信号、８：リセツト信号、９：メモリセレクト
信号、１０：リセツト番地アクセス信号、１１：
本考案により発生されるリセツト信号。
FIG. 1 is a schematic configuration diagram of an electronic device including a reset device showing one embodiment of the present invention, and FIG.
This is an operation time chart shown in the figure. 1: CPU, 2: Reset address decoder, 3:
One-shot pulse generation circuit, 4: OR circuit, 5
: Reset memory, 6: Address bus, 7: Read signal, 8: Reset signal, 9: Memory select signal, 10: Reset address access signal, 11:
Reset signal generated by the present invention.
Claims (1)
ト後の命令が格納されているリセツトメモリ、該
リセツトメモリに接続され、リセツト番地をデコ
ードするリセツト番地デコーダ、該リセツト番地
デコーダからの信号入力に従つてパルスを発生す
るパルス発生回路、およびＣＰＵからのリセツト
信号と該パルスの論理和をとるＯＲ回路を設け、
ＣＰＵがリセツト番地をアクセスするだけで、周
辺装置等に対するリセツト信号を送出することを
特徴とするリセツト装置。 In an electronic device using a CPU, there is a reset memory in which instructions after a reset are stored, a reset address decoder connected to the reset memory to decode the reset address, and a pulse generated in accordance with a signal input from the reset address decoder. A pulse generating circuit is provided, and an OR circuit is provided to logically OR the reset signal from the CPU and the pulse.
A reset device characterized in that a reset signal is sent to peripheral devices etc. simply by a CPU accessing a reset address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5420685U JPS61172325U (en) | 1985-04-11 | 1985-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5420685U JPS61172325U (en) | 1985-04-11 | 1985-04-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61172325U true JPS61172325U (en) | 1986-10-25 |
Family
ID=30575758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5420685U Pending JPS61172325U (en) | 1985-04-11 | 1985-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61172325U (en) |
-
1985
- 1985-04-11 JP JP5420685U patent/JPS61172325U/ja active Pending
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