JPS62175352U - - Google Patents

Info

Publication number
JPS62175352U
JPS62175352U JP5996486U JP5996486U JPS62175352U JP S62175352 U JPS62175352 U JP S62175352U JP 5996486 U JP5996486 U JP 5996486U JP 5996486 U JP5996486 U JP 5996486U JP S62175352 U JPS62175352 U JP S62175352U
Authority
JP
Japan
Prior art keywords
control
hardware
information
memory address
control information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5996486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5996486U priority Critical patent/JPS62175352U/ja
Publication of JPS62175352U publication Critical patent/JPS62175352U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるマイクロ命
令制御装置の概略構成を示す構成図、第2図は従
来のマイクロ命令制御装置を示す構成図である。 図において、1はアドレスレジスタ、2は制御
記憶部、4a〜4dはハードウエア、7は制御信
号生成回路。なお、図中、同一符号は同一又は相
当部分を示す。
FIG. 1 is a block diagram showing a schematic structure of a microinstruction control device according to an embodiment of the invention, and FIG. 2 is a block diagram showing a conventional microinstruction control device. In the figure, 1 is an address register, 2 is a control storage section, 4a to 4d are hardware, and 7 is a control signal generation circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アドレスレジスタより送出されたメモリアドレ
ス情報よりハードウエアに対する制御信号を生成
し出力する制御信号生成回路と、上記メモリアド
レス情報に基づいて上記ハードウエアに対する制
御情報を読み出す制御記憶部とを備え、これら制
御信号と制御情報とを1つのハードウエア制御情
報として合成することを特徴とするマイクロ命令
制御装置。
It is equipped with a control signal generation circuit that generates and outputs a control signal for the hardware from memory address information sent from the address register, and a control storage section that reads out control information for the hardware based on the memory address information. A microinstruction control device characterized by combining a signal and control information as one piece of hardware control information.
JP5996486U 1986-04-21 1986-04-21 Pending JPS62175352U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5996486U JPS62175352U (en) 1986-04-21 1986-04-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5996486U JPS62175352U (en) 1986-04-21 1986-04-21

Publications (1)

Publication Number Publication Date
JPS62175352U true JPS62175352U (en) 1987-11-07

Family

ID=30891958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5996486U Pending JPS62175352U (en) 1986-04-21 1986-04-21

Country Status (1)

Country Link
JP (1) JPS62175352U (en)

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