JPS60111598U

JPS60111598U - memory element

Info

Publication number: JPS60111598U
Application number: JP20392483U
Authority: JP
Inventors: 篤志小川
Original assignee: 日本電気株式会社
Priority date: 1983-12-28
Filing date: 1983-12-28
Publication date: 1985-07-29

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のアドレスマルチ方式記憶素子の一例のブ
ロック図、第２図は第１図に示す記憶素子に入力される
信号の波形図、第３図は第１図に示す記憶素子を用いた
記憶装置の要部のブロック図、第４図は本考案の一実施
例のブロック図、第５図は第４図に示す実施例を用いた
記憶装置の要部のブロック図である。１０・・・記憶素子、１１，１１’・・・行アドレス系
制御回路、１２・・・行アドレスラッチ回路、１３・・
・行デコーダ、１４，１４’・・・列アドレス系制御回
路、１５・・・列アドレスラッチ回路、１６川列デコー
ダ、１７・・・メモリセルアレイ、２１・・・高速クロ
ック分周回路、２２・・・分周回路、２３・・・クロッ
ク合成回路、２’４，２４’・・・アドレス切換回路、
３０・・・記憶素子、３１・・・出力バッファ、３２・
・・インバータ、３３・・・出力端子、３４・・・行ア
ドレス読込み終了信号、３５・・・行デコーダ活性化信
号、Ａ。〜Ａｍ−・・アドレス入力端子、ｑ・・・メモリ要求信
号。Figure 1 is a block diagram of an example of a conventional multi-address storage element, Figure 2 is a waveform diagram of a signal input to the memory element shown in Figure 1, and Figure 3 is a block diagram of an example of a conventional multi-address storage element. FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is a block diagram of essential parts of a storage device using the embodiment shown in FIG. 10...Storage element, 11, 11'...Row address system control circuit, 12...Row address latch circuit, 13...
・Row decoder, 14, 14'... Column address system control circuit, 15... Column address latch circuit, 16 column decoder, 17... Memory cell array, 21... High speed clock frequency dividing circuit, 22. ...Frequency divider circuit, 23...Clock synthesis circuit, 2'4,24'...Address switching circuit,
30...Storage element, 31...Output buffer, 32.
. . . Inverter, 33 . . . Output terminal, 34 . . . Row address read end signal, 35 . . . Row decoder activation signal, A. ~Am-...address input terminal, q...memory request signal.

Claims

[Scope of utility model registration request]

A memory cell array, a row decoder and a column decoder that decode address signals applied to the memory cell array, a row address latch circuit and a column address latch circuit that latch row and column addresses, and the row address latch circuit decodes row address signals. a row address system control circuit that outputs a row address read end signal to the outside when the latch of the row address is completed;
A memory element comprising: a column address system control circuit that inputs the row address read end signal via an inverter to control a column address system.