JPS62164693U

JPS62164693U -

Info

Publication number: JPS62164693U
Application number: JP5326086U
Authority: JP
Priority date: 1986-04-09
Filing date: 1986-04-09
Publication date: 1987-10-19

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は従来の装置を示すブロツク図、第３図
は第１図に示す装置の各部の信号を示す動作タイ
ムチヤート。１はメモリ、２Ａは第１のフリツプフロツプ、
２Ｂは第２のフリツプフロツプ、３はゲート回路
、１０はアドレス信号、１１はデータ入力信号、
１２は書込み信号、１３は書込みサイクル指示信
号、１４はクロツク信号、１５はデータ出力信号
、１８はエラー信号。尚、各図中同一符号は同一
又は相当部分を示す。 FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a block diagram showing a conventional device, and FIG. 3 is an operation time chart showing signals of various parts of the device shown in FIG. 1 is a memory, 2A is a first flip-flop,
2B is a second flip-flop, 3 is a gate circuit, 10 is an address signal, 11 is a data input signal,
12 is a write signal, 13 is a write cycle instruction signal, 14 is a clock signal, 15 is a data output signal, and 18 is an error signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Claims for Utility Model Registration] In a memory device that writes a data input signal to a memory location specified by an input address signal or reads data stored in the memory location as a data output signal, A write cycle indication signal is connected to the signal input terminal, with a logic "1" indicating a write cycle and a logic "0" indicating a read cycle, and a write signal controlling writes to the memory device. a first flip-flop connected to a clock signal input terminal; means for resetting the first flip-flop by a clock signal indicating the start point of a write cycle and a read cycle of the write cycle instruction signal; A gate circuit that outputs an exclusive OR with a write cycle instruction signal, a second flip-flop that latches the output of the gate circuit using the clock signal, and means for making the output of the second flip-flop an error signal. A memory device characterized by: