JPS5617417A - Common bus supervisory system - Google Patents

Common bus supervisory system

Info

Publication number
JPS5617417A
JPS5617417A JP9226179A JP9226179A JPS5617417A JP S5617417 A JPS5617417 A JP S5617417A JP 9226179 A JP9226179 A JP 9226179A JP 9226179 A JP9226179 A JP 9226179A JP S5617417 A JPS5617417 A JP S5617417A
Authority
JP
Japan
Prior art keywords
error
bus
history memory
memory
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9226179A
Other languages
Japanese (ja)
Other versions
JPS5759569B2 (en
Inventor
Hidekiyo Ozawa
Koichi Okamoto
Yasuyoshi Asaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9226179A priority Critical patent/JPS5617417A/en
Publication of JPS5617417A publication Critical patent/JPS5617417A/en
Publication of JPS5759569B2 publication Critical patent/JPS5759569B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To make efficient use of a common bus and histroy memory by holding the previous memory contents without writing the history memory while a bus error signal is sent onto the common bus.
CONSTITUTION: Once a transfer unit that writes information in history memory HM detects a parity error occurring, a bus error signal is generated on bus signal line l4. Then, history memory HM is inhibited from being written. At this time, central processor CPU reads history memory HM to know whether the error has resided on the bus or to sense the error state of an error-occurring unit by way of common buses l1 and l1', thereby performing error processing afterward. If the bus error signal is reset in sensing the error, writing history memory HM is restarted.
COPYRIGHT: (C)1981,JPO&Japio
JP9226179A 1979-07-20 1979-07-20 Common bus supervisory system Granted JPS5617417A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9226179A JPS5617417A (en) 1979-07-20 1979-07-20 Common bus supervisory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9226179A JPS5617417A (en) 1979-07-20 1979-07-20 Common bus supervisory system

Publications (2)

Publication Number Publication Date
JPS5617417A true JPS5617417A (en) 1981-02-19
JPS5759569B2 JPS5759569B2 (en) 1982-12-15

Family

ID=14049457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9226179A Granted JPS5617417A (en) 1979-07-20 1979-07-20 Common bus supervisory system

Country Status (1)

Country Link
JP (1) JPS5617417A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614868A (en) * 1992-08-31 1994-01-25 Olympus Optical Co Ltd Endoscope system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62144482U (en) * 1986-03-08 1987-09-11
JPH0652453U (en) * 1991-04-12 1994-07-19 稔 西村 High sensitivity delicate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614868A (en) * 1992-08-31 1994-01-25 Olympus Optical Co Ltd Endoscope system

Also Published As

Publication number Publication date
JPS5759569B2 (en) 1982-12-15

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