JPS5513426A - Checking system for data bus - Google Patents
Checking system for data busInfo
- Publication number
- JPS5513426A JPS5513426A JP8468378A JP8468378A JPS5513426A JP S5513426 A JPS5513426 A JP S5513426A JP 8468378 A JP8468378 A JP 8468378A JP 8468378 A JP8468378 A JP 8468378A JP S5513426 A JPS5513426 A JP S5513426A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- pcg
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE: To simplify the constitution of both input card ICD and output card OCD by installing the input signal buffer and parity checker generator at the input/ output interface part.
CONSTITUTION: For example, the data on inner data bus IBUS is delivered to input/output signal data bus SBUS via bus open gate signal BOG at the signal output time, and parity bit PB is applied to generator PCG. Common buffer register CBF reads out the output data on SBUS and then delivers it to PCG for checking. In case some error takes place, the prescribed signal is applied to defect process circuit DET when writing signal WT is applied to gate G13, thus giving the alarm. The input sent from input card ICD is set temporarily to common buffer register CBF of input/output interface part INT and then sent out to IBUS after addition of PB via PCG. In such way, the units which can be used in common are collected, thus simplifying the input and output cards.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53084683A JPS5835284B2 (en) | 1978-07-12 | 1978-07-12 | Data bus check method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53084683A JPS5835284B2 (en) | 1978-07-12 | 1978-07-12 | Data bus check method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5513426A true JPS5513426A (en) | 1980-01-30 |
JPS5835284B2 JPS5835284B2 (en) | 1983-08-02 |
Family
ID=13837480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53084683A Expired JPS5835284B2 (en) | 1978-07-12 | 1978-07-12 | Data bus check method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5835284B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5872254A (en) * | 1981-10-26 | 1983-04-30 | Nec Corp | Parity checking and parity bit generating circuit |
JPS61117652A (en) * | 1984-10-29 | 1986-06-05 | Fujitsu Ltd | Hierarchical bus control system |
JPS6257048A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
JPS6257049A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
US6221760B1 (en) * | 1997-10-20 | 2001-04-24 | Nec Corporation | Semiconductor device having a silicide structure |
-
1978
- 1978-07-12 JP JP53084683A patent/JPS5835284B2/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5872254A (en) * | 1981-10-26 | 1983-04-30 | Nec Corp | Parity checking and parity bit generating circuit |
JPS61117652A (en) * | 1984-10-29 | 1986-06-05 | Fujitsu Ltd | Hierarchical bus control system |
JPS6257048A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
JPS6257049A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
US6221760B1 (en) * | 1997-10-20 | 2001-04-24 | Nec Corporation | Semiconductor device having a silicide structure |
Also Published As
Publication number | Publication date |
---|---|
JPS5835284B2 (en) | 1983-08-02 |
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