JPS5872254A - Parity checking and parity bit generating circuit - Google Patents

Abstract

PURPOSE:To improve reliability and simplify justification check by using a parity generating circuit under time division at the time of parity check and parity bit generation. CONSTITUTION:In a parity checking and parity bit generating circuit for data on a bilateral bus, only a parity bit 7 is outputted out of a data consisting of a data bit 6 and the parity bit 7 at the time of parity check. At the time of parity bit generation, logic ''0'' outputted from a switching circuit 1 and the data bit 6 are inputted to a parity generating circuit 2, an odd parity is outputted also for the data bit 6 and the parity bit 7 and a parity 8 is outputted. If there is no parity error in the data, logic ''0'' is outputted and a parity error causes the circuit to output logic ''1''. Thus the same parity generating circuit 2 can be used under time division at the time of parity check and parity generation, reducing hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity check and parity bit generation circuit, and particularly to a parity check and parity bit generation circuit suitable for data on a bidirectional bus.

This type of conventional parity check/parity bit generation circuit generates parity from data bits of the data and corresponding parity bits with the same odd (even) parity as the data during the parity check. a parity error indicating circuit which sets the output of the first parity generating circuit to indicate that there is a parity error as a result of the parity check; and a second parity generation circuit that generates parity from the data bits of the data and outputs the parity to the corresponding parity bit position of the data. In other words, it is no different from the parity check and parity pit generation circuit for data on the directional bus.

In such a conventional configuration, a large amount of hardware is required during parity check and when parity pits are generated (in other words, parity generation is performed in separate parity generation circuits). The disadvantage is that the reliability of S-ware is low, and that it is troublesome to check the validity of these S-ware operations.

SUMMARY OF THE INVENTION An object of the present invention is to perform a validity check of an 1lt1 operation in a timely manner with high reliability, and to provide a test and parity generation circuit having a simple configuration.

In the circuit SSa of the present invention, in the parity check and parity pit generation circuit for data on a bidirectional path, the parity pit of the data is output during the parity check, and the parity bit is output as "0" when the parity bit occurs.
a parity generation circuit that generates parity from the output of the switching circuit and the data bits of the data with the same odd (even) parity as the data; a parity error display circuit which is set when the output of the cough gate circuit has a logic "1" to indicate that there is a parity error as a result of the parity check; and m parity occurrences when the parity pit occurs. The present invention is characterized in that it includes a supply circuit that outputs the parity generated by the circuit to a corresponding parity pit position of the data.

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, this implementation column includes a multiplexer l, which is a switching circuit, and a parity generation circuit 2.

AND circuit 3 which is a gate circuit and JK which is a display circuit
It consists of a 7-lip flop 4 and a three-state circuit 5 which is a supply circuit. Reference numerals 6 and 7 are the eight data bits and corresponding parity pits of the data on the bidirectional bus, respectively, and reference numeral 8 is a parity error signal.

FIG. 2 shows a portion of a logical device to which this embodiment is applied.

Accumulation 11) ACC is a register with a parity bit)
The reception of data with the can register in the logic scissors plays a central role in performing the transfer. General purpose register GPRFiN@
It is a register bank with a stack structure. The arithmetic unit ALU performs accumulation by the operation of the multiplexer MPX.
ACC and general register bank or general register GP
Performs an operation with R and registers REG11. R
EGI2゜...REGIM outputs the status of the logic device etc. to the accumulation @ACC via bidirectional bus B, and registers REG21. REG22. ...REG2
N receives data from the accumulator CC via the bidirectional bus Bt, and performs control specific to the logic device, such as controlling peripheral devices, and the reference symbol PCG is the implementation column shown in the first @. Then, a parity check and parity pit generation are performed on the data on the bidirectional path B.

First, the contents of the accumulation @ACC are stored in the register REGzX(x,
=1 to N) will be explained by returning to FIG. 1 again. In this case, the parity check/parity pit generation circuit FCG performs a parity check.

Since the successive signal RED is the logic rOJ, it enters a Munby dance state and has no effect on the severity pit 7.

In the parity generation circuit 2, since the data consisting of data bits 6 and parity pits 7 has an odd parity, the parity generation circuit 2
Even for parity pit 7, odd parity and parity are output. Therefore, if the above data does not have a parity 2-, the output of the parity generation circuit 2 will be a logic "
0", and if there is a parity error, it becomes logic "l".

Write signal WRT to AND circuit 3 Hiro, Cu @A
When writing the contents of CC to the register EG2X or when checking the validity of the operation of this embodiment, the logic rx
The output of the JK parity generation circuit 2 is output to the JK7 logic flop 4.

In this way, if there is a parity error in the above-mentioned data, the JKy flip-flop 4 is set to indicate this fact.

Next, accumulate the contents of REGIY (Y-1-M) @A
The case of reading to CC will be explained. In this case, Mori,
A parity check/parity bit generation circuit PCG generates a parity bit.

Since the continuation signal RED is logic "1", multiplexer 1 outputs logic "0" to parity generation circuit 2. Therefore, the parity generation circuit 2 substantially eliminates the odd parity of only the data bit 6 and outputs the parity. This parity is passed through the three-state circuit 5 whose output is in a low impedance state to become a parity pit 7, and a parity bit for data bit 6 is generated.

Finally, the validity of the operation of the fifth embodiment can be checked as follows. First, in the write mode, the parity generated by the parity generation circuit 2 for the known data bit 6 and parity pit 7 is obtained as the output of the JK7 lip-flop 4.

A microinstruction compares this output with the parity obtained from the known data described above. Next, the parity t generated by the parity generation circuit 2 from the known data bit 6 is set to continuous output mode, and the parity t generated by the parity generation circuit 2 is set to J by operating the AND circuit 3.
It is obtained as the output of K-flip 70 and is compared by the microinstruction in the same manner as in write mode.

In this embodiment, a case has been described in which odd parity is set for the data on the bidirectional path, but this does not apply to the present invention, and even parity may be set. In that case, the parity generation circuit 2
There is also a need for even parity.

i9. In this embodiment column, only 1-byte data has been described, but by providing this embodiment column for the number of bytes, an embodiment for data of multiple bytes can be easily constructed.

According to the present invention, in a parity check and parity bit generation circuit for data on a bidirectional path, the parity check and parity bit generation are performed by separate parity generation circuits, as described above. a switching circuit that outputs a parity pit of the data during inspection and outputs logic "0" when the parity bit occurs;

a parity generation circuit that generates parity with the same odd (even) parity as the data from the output of the switching circuit and the data bits of the data; and a parity generation circuit that outputs the parity at the time of the parity check. a parity error display circuit that is set to indicate that there is a parity error as a result of the parity check by setting logic rlJ at the output of the gate circuit and the gate circuit; and il! By providing a supply circuit that outputs the parity generated by the parity generation circuit to the parity bit position of the data when the parity bit is generated, the same parity generation circuit can be used both during parity check and when generating the parity bit. This reduces the amount of hardware so that it can be used separately, and therefore the hardware can be used separately.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of application of this embodiment. In the figure, l, MPX... multiplexer. 2... Parity (generation circuit, 3... AND circuit, 4... JK7 logic flop, 5... old... three-fold trend circuit. 6... data Bit, 7...Parity pit, 8...Parity error signal, PCG.
...Parity check and parity bit generation circuit, A
CC... Accumulator. GPR・・・General purpose register, human LU・・・・・・
Arithmetic unit, REGI 1, REGI 2,...
...REGIM, REG2t, REG22. ...
...REG2N/song/register, B...bidirectional path, RED/song/read signal, WRT...
-Write signal, "0"...Logic "0".

Claims (1)

[Claims] A parity check and parity bit generation circuit for data on a bidirectional bus includes a switching circuit that outputs a parity bit of the data during a # parity check and outputs a logic "0" when the parity bit is generated; A parity generation circuit that generates parity from the output of the switching circuit and the data bits of the data with the same odd (even) parity as the data and %cough parity. t
I. A gate circuit that outputs an output during a parity check; a parity error imposing circuit that is set to have a logic "l" at the output of the gate circuit to indicate that there is a parity error as a result of the parity check; and the parity bit. At the time of generation, the parity t generated by the parity generation circuit - the parity value corresponding to the data