JPS5685162A - Data input circuit - Google Patents

Data input circuit

Info

Publication number
JPS5685162A
JPS5685162A JP16301479A JP16301479A JPS5685162A JP S5685162 A JPS5685162 A JP S5685162A JP 16301479 A JP16301479 A JP 16301479A JP 16301479 A JP16301479 A JP 16301479A JP S5685162 A JPS5685162 A JP S5685162A
Authority
JP
Japan
Prior art keywords
signal
gate
data processor
error
turns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16301479A
Other languages
Japanese (ja)
Inventor
Tetsuro Katagiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16301479A priority Critical patent/JPS5685162A/en
Publication of JPS5685162A publication Critical patent/JPS5685162A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent reading of an ineffective data for a data processor, by sending an address answer signal back to a data processor after receiving an address signal delivered from the data processor and checking an error of the data.
CONSTITUTION: When the gate signal G1 becomes e.g. "1", the signal S1 is turned into the signal D on the common bus 2a via the input gate circuit 1-1 to be then delivered to the process input 3 as well as to the error check circuit 8 for checking. As a result, the signal 8a is turned into "1" in case the signal D contains no error and then into "0" in case the signal D contains some error respectively. On the other hand, the reception detecting circuit 7-1 receives the gate signal D and then turns it into "1". Thus the AND gate 9 turns the output into "1" if the signal 8a is turned to "1" at that moment. Accordingly, the data processor 2 reads the signal D on the common bus as an effective one only when the output of the gate 9 turns to "1" after an output of the address signal.
COPYRIGHT: (C)1981,JPO&Japio
JP16301479A 1979-12-12 1979-12-12 Data input circuit Pending JPS5685162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16301479A JPS5685162A (en) 1979-12-12 1979-12-12 Data input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16301479A JPS5685162A (en) 1979-12-12 1979-12-12 Data input circuit

Publications (1)

Publication Number Publication Date
JPS5685162A true JPS5685162A (en) 1981-07-11

Family

ID=15765548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16301479A Pending JPS5685162A (en) 1979-12-12 1979-12-12 Data input circuit

Country Status (1)

Country Link
JP (1) JPS5685162A (en)

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