JPS5525117A - Check circuit for signal group - Google Patents

Check circuit for signal group

Info

Publication number
JPS5525117A
JPS5525117A JP9720078A JP9720078A JPS5525117A JP S5525117 A JPS5525117 A JP S5525117A JP 9720078 A JP9720078 A JP 9720078A JP 9720078 A JP9720078 A JP 9720078A JP S5525117 A JPS5525117 A JP S5525117A
Authority
JP
Japan
Prior art keywords
signal
rom12
signals
dout
normal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9720078A
Other languages
Japanese (ja)
Inventor
Shigeru Kaneko
Yoshio Kiryu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9720078A priority Critical patent/JPS5525117A/en
Publication of JPS5525117A publication Critical patent/JPS5525117A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To detect the occurrence of an error in a signal group by an overflow signal from newly-provided ROM where a group of signals to be checked are stored according to addresses.
CONSTITUTION: Signals S1 to S5 to be checked are connected to memory address input A0 to A4 of ROM12 and its read output Dout becomes an erroe output signal as it is. The signal of "0" indicates that signals S2 to S5 are all normal and the signal of "1" that one of them is abnormal. Table 1 shows the memory contents of ROM12. Talking about signal S1 of "1" with normal operations of buffer gates 1 to 5, the memory addresses of ROM12 are all "1" since S1 to S5 are all "1", and Dout is "0", so that it will be indicated that S2 to S5 are normal. When gate 1 gets out of order, on the other hand, S1 is "1" while S2 to S5 are "0", the memory address of ROM12 is "10000" and Dout is "1", thereby detecting the fault.
COPYRIGHT: (C)1980,JPO&Japio
JP9720078A 1978-08-11 1978-08-11 Check circuit for signal group Pending JPS5525117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9720078A JPS5525117A (en) 1978-08-11 1978-08-11 Check circuit for signal group

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9720078A JPS5525117A (en) 1978-08-11 1978-08-11 Check circuit for signal group

Publications (1)

Publication Number Publication Date
JPS5525117A true JPS5525117A (en) 1980-02-22

Family

ID=14185952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9720078A Pending JPS5525117A (en) 1978-08-11 1978-08-11 Check circuit for signal group

Country Status (1)

Country Link
JP (1) JPS5525117A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984004984A1 (en) * 1983-06-03 1984-12-20 Sony Corp Majority circuit
JPS648465A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Tri-state bus circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984004984A1 (en) * 1983-06-03 1984-12-20 Sony Corp Majority circuit
JPS648465A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Tri-state bus circuit

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