JPS56148789A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS56148789A
JPS56148789A JP5277380A JP5277380A JPS56148789A JP S56148789 A JPS56148789 A JP S56148789A JP 5277380 A JP5277380 A JP 5277380A JP 5277380 A JP5277380 A JP 5277380A JP S56148789 A JPS56148789 A JP S56148789A
Authority
JP
Japan
Prior art keywords
circuit
output
short
decoder
erroneous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5277380A
Other languages
Japanese (ja)
Other versions
JPS5912000B2 (en
Inventor
Shigenobu Sakai
Shigeto Koda
Hideo Kikuchi
Yoshitaka Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55052773A priority Critical patent/JPS5912000B2/en
Publication of JPS56148789A publication Critical patent/JPS56148789A/en
Publication of JPS5912000B2 publication Critical patent/JPS5912000B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent the output of erroneous readout information by invalidating readout information from a storage cell through detecting short-circuit defection, etc., between an address buffer and decoder. CONSTITUTION:Addresses Cq and Cq' from address buffer 1 are applied to exclusive NOR circuit Pq of detecting circuit 7, whose output is applied to the set terminal of RST type FF via OR circuit 9. Consequently, the set output of FF12 is inverted to the high level because addresses Cq and Cq' are the same signal if output line Bq between buffer 1 and decoder 2 is short-circuited or almost short-circuited, so that output-side AND gate 13 of information invalidating circuit 8 will be released via inverter 14. Therefore, the output of erroneous readout information from multiplexer 4 of storage cell storage circuit 3 is prevented. Further, the same effection is obtained by inhibiting the application of an erroneous address due to a short circuit to the decoder.
JP55052773A 1980-04-21 1980-04-21 semiconductor storage device Expired JPS5912000B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55052773A JPS5912000B2 (en) 1980-04-21 1980-04-21 semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55052773A JPS5912000B2 (en) 1980-04-21 1980-04-21 semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS56148789A true JPS56148789A (en) 1981-11-18
JPS5912000B2 JPS5912000B2 (en) 1984-03-19

Family

ID=12924177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55052773A Expired JPS5912000B2 (en) 1980-04-21 1980-04-21 semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5912000B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154244A (en) * 1987-12-10 1989-06-16 Nec Corp Logical integrated circuit
CN105914736A (en) * 2016-05-05 2016-08-31 河海大学 Inverter power supply modeling method in power distribution network short circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154244A (en) * 1987-12-10 1989-06-16 Nec Corp Logical integrated circuit
CN105914736A (en) * 2016-05-05 2016-08-31 河海大学 Inverter power supply modeling method in power distribution network short circuit

Also Published As

Publication number Publication date
JPS5912000B2 (en) 1984-03-19

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