JPS5641600A - Detection system for memory capacity - Google Patents

Detection system for memory capacity

Info

Publication number
JPS5641600A
JPS5641600A JP11766879A JP11766879A JPS5641600A JP S5641600 A JPS5641600 A JP S5641600A JP 11766879 A JP11766879 A JP 11766879A JP 11766879 A JP11766879 A JP 11766879A JP S5641600 A JPS5641600 A JP S5641600A
Authority
JP
Japan
Prior art keywords
register
memory
block
memory capacity
detection system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11766879A
Other languages
Japanese (ja)
Inventor
Makoto Nakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11766879A priority Critical patent/JPS5641600A/en
Publication of JPS5641600A publication Critical patent/JPS5641600A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To facilitate a read of the memory capacity of hardware at a firmware side by combining a free gate in a memory block with a register.
CONSTITUTION: Memory block 101 consists of memory 11 and memory control circuit 12, which is connected to MPU bus 14 via register 13 together with control circuits of the same constitution of blocks 102W10n. Then, register 13 shows a constant logical level when a block is connected and makes it possible to record its inverted level when not. Thus, the contents of register 13 are read out at the firmware side, so that the block can immediately be judged. In this case, logic gates 211W213 in circuit 12 are used for data control and free gate 214 is coupled with register 13.
COPYRIGHT: (C)1981,JPO&Japio
JP11766879A 1979-09-13 1979-09-13 Detection system for memory capacity Pending JPS5641600A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11766879A JPS5641600A (en) 1979-09-13 1979-09-13 Detection system for memory capacity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11766879A JPS5641600A (en) 1979-09-13 1979-09-13 Detection system for memory capacity

Publications (1)

Publication Number Publication Date
JPS5641600A true JPS5641600A (en) 1981-04-18

Family

ID=14717318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11766879A Pending JPS5641600A (en) 1979-09-13 1979-09-13 Detection system for memory capacity

Country Status (1)

Country Link
JP (1) JPS5641600A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58111168A (en) * 1981-12-25 1983-07-02 Canon Inc Information transmitting device
JPS58501972A (en) * 1981-11-17 1983-11-17 ヒュンダイ・エレクトロニクス・インダストリーズ・カンパニー・リミテッド memory mapping unit
JPH0262646A (en) * 1988-08-30 1990-03-02 Nec Corp Multi-firmware device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501972A (en) * 1981-11-17 1983-11-17 ヒュンダイ・エレクトロニクス・インダストリーズ・カンパニー・リミテッド memory mapping unit
JPS58111168A (en) * 1981-12-25 1983-07-02 Canon Inc Information transmitting device
JPH022235B2 (en) * 1981-12-25 1990-01-17 Canon Kk
JPH0262646A (en) * 1988-08-30 1990-03-02 Nec Corp Multi-firmware device

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