JPS55139699A - Error detection system of memory unit - Google Patents

Error detection system of memory unit

Info

Publication number
JPS55139699A
JPS55139699A JP4765279A JP4765279A JPS55139699A JP S55139699 A JPS55139699 A JP S55139699A JP 4765279 A JP4765279 A JP 4765279A JP 4765279 A JP4765279 A JP 4765279A JP S55139699 A JPS55139699 A JP S55139699A
Authority
JP
Japan
Prior art keywords
information
pieces
coincidence
detection system
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4765279A
Other languages
Japanese (ja)
Inventor
Kazunari Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4765279A priority Critical patent/JPS55139699A/en
Publication of JPS55139699A publication Critical patent/JPS55139699A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to detect even an error of an even-numbered bit by a parity check, by checking coincidence between input information and output information through exclusive OR.
CONSTITUTION: Pieces of input information A1... written in logic memory units 1... and pieces of output information B1... read from units 1 are exclusively OR-ed to generate pieces of ineffective coincidence information C1... between pieces of input and output information from exclusive OR units 2... Then, they are applied to AND gate 4 opening by a needed timing signal by way of OR circuit 3 to generate coincidence or dissidence information F, so that a parity check on even an error of an even-numbered bit can be made.
COPYRIGHT: (C)1980,JPO&Japio
JP4765279A 1979-04-18 1979-04-18 Error detection system of memory unit Pending JPS55139699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4765279A JPS55139699A (en) 1979-04-18 1979-04-18 Error detection system of memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4765279A JPS55139699A (en) 1979-04-18 1979-04-18 Error detection system of memory unit

Publications (1)

Publication Number Publication Date
JPS55139699A true JPS55139699A (en) 1980-10-31

Family

ID=12781175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4765279A Pending JPS55139699A (en) 1979-04-18 1979-04-18 Error detection system of memory unit

Country Status (1)

Country Link
JP (1) JPS55139699A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02142223A (en) * 1988-11-24 1990-05-31 Fujitsu Ltd Parity check circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02142223A (en) * 1988-11-24 1990-05-31 Fujitsu Ltd Parity check circuit

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