JPS5792499A - Directory device - Google Patents

Directory device

Info

Publication number
JPS5792499A
JPS5792499A JP55167435A JP16743580A JPS5792499A JP S5792499 A JPS5792499 A JP S5792499A JP 55167435 A JP55167435 A JP 55167435A JP 16743580 A JP16743580 A JP 16743580A JP S5792499 A JPS5792499 A JP S5792499A
Authority
JP
Japan
Prior art keywords
signal line
parity
information
output signal
comparing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55167435A
Other languages
Japanese (ja)
Inventor
Keizo Aoyanagi
Takashi Hiraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55167435A priority Critical patent/JPS5792499A/en
Publication of JPS5792499A publication Critical patent/JPS5792499A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

PURPOSE:To prevent erroneous operation easily and to attain each access correctly and efficiently by making a parity check on directly information by providing only a parity generating circuit and a comparing circuit. CONSTITUTION:A comparing circuit 19 compares a parity bit on a parity output signal line 15 with that on a readout output signal line 18. When dissidence is detected, an inhibition signal is outputted to an inhibition signal line 20. A comparing circuit 21, even when detecting the coincidence between information on an output signal line 12 and that on a readout output signal line 17, is inhibited by the inhibition signal on the signal line 20 from outputting a coincidence detection signal. Consequently, a cash error is judged to be generated and a CPU reads data in a prescribed address correctly. In this case, directory information which corresponds to the address and a parity bit generated by a parity generating circuit 14 on the basis of the information are registered in a directory memory 16 and the data is retained in a cash memory.
JP55167435A 1980-11-28 1980-11-28 Directory device Pending JPS5792499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55167435A JPS5792499A (en) 1980-11-28 1980-11-28 Directory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55167435A JPS5792499A (en) 1980-11-28 1980-11-28 Directory device

Publications (1)

Publication Number Publication Date
JPS5792499A true JPS5792499A (en) 1982-06-09

Family

ID=15849646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55167435A Pending JPS5792499A (en) 1980-11-28 1980-11-28 Directory device

Country Status (1)

Country Link
JP (1) JPS5792499A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59213097A (en) * 1983-05-18 1984-12-01 Hitachi Ltd Data processing device
JPS62212751A (en) * 1986-03-14 1987-09-18 Hitachi Ltd Data processor
JPH0244944U (en) * 1988-09-14 1990-03-28
JPH05100953A (en) * 1991-10-09 1993-04-23 Pfu Ltd Cache memory control system
US7010740B1 (en) * 2001-05-17 2006-03-07 Emc Corporation Data storage system having no-operation command
JP2006527871A (en) * 2003-06-18 2006-12-07 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング Method and apparatus for recognizing errors for cache memory, and cache memory
US7716416B2 (en) 2003-07-29 2010-05-11 Fujitsu Limited Analysis for a multiple tag hit in a content addressable memory (CAM)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59213097A (en) * 1983-05-18 1984-12-01 Hitachi Ltd Data processing device
JPS62212751A (en) * 1986-03-14 1987-09-18 Hitachi Ltd Data processor
JPH0244944U (en) * 1988-09-14 1990-03-28
JPH05100953A (en) * 1991-10-09 1993-04-23 Pfu Ltd Cache memory control system
US7010740B1 (en) * 2001-05-17 2006-03-07 Emc Corporation Data storage system having no-operation command
JP2006527871A (en) * 2003-06-18 2006-12-07 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング Method and apparatus for recognizing errors for cache memory, and cache memory
JP4773343B2 (en) * 2003-06-18 2011-09-14 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング Method and apparatus for recognizing errors for cache memory, and cache memory
US7716416B2 (en) 2003-07-29 2010-05-11 Fujitsu Limited Analysis for a multiple tag hit in a content addressable memory (CAM)

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