JPS5750308A - Time base correcting device - Google Patents
Time base correcting deviceInfo
- Publication number
- JPS5750308A JPS5750308A JP55123348A JP12334880A JPS5750308A JP S5750308 A JPS5750308 A JP S5750308A JP 55123348 A JP55123348 A JP 55123348A JP 12334880 A JP12334880 A JP 12334880A JP S5750308 A JPS5750308 A JP S5750308A
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- inputted
- supplied
- wdt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Television Signal Processing For Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To perform the error correction processing correctly, by adding an error flag to data after one block of data is read out. CONSTITUTION:A reproduced data WDT is supplied to a delay circuit 42 and a CRC checker 43, and output data WDT' from the circuit 42, a write control pulse WE' from an FF50 to which an error detection signal EDT is inputted from the checker 43, and an address from an address selector 44 are inputted to an RAM40, and data RD is outputted. Data WDT' and a read block address RA are inputted to an ROM51, and a write block address WA is supplied to the selector 44. Input data is supplied from a multiplexer 53 to a memory 52, and an error flag EFLG is outputted through a latch 54. The output and read data RDT are synchronous with each other, and 1 is written in the address. Thus, error correction is performed correctly.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55123348A JPS5750308A (en) | 1980-09-05 | 1980-09-05 | Time base correcting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55123348A JPS5750308A (en) | 1980-09-05 | 1980-09-05 | Time base correcting device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5750308A true JPS5750308A (en) | 1982-03-24 |
JPH0158578B2 JPH0158578B2 (en) | 1989-12-12 |
Family
ID=14858335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55123348A Granted JPS5750308A (en) | 1980-09-05 | 1980-09-05 | Time base correcting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5750308A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0117756A2 (en) * | 1983-02-25 | 1984-09-05 | Nec Corporation | Data interpolating circuit |
JPS6050667A (en) * | 1983-08-27 | 1985-03-20 | Sony Corp | Optical disc recording device |
US5163053A (en) * | 1988-10-24 | 1992-11-10 | Matsushita Electric Industrial Co., Ltd. | Audio signal demodulation circuit |
US5363384A (en) * | 1988-10-24 | 1994-11-08 | Matsushita Electric Industrial, Co., Ltd. | Audio signal demodulation circuit |
-
1980
- 1980-09-05 JP JP55123348A patent/JPS5750308A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0117756A2 (en) * | 1983-02-25 | 1984-09-05 | Nec Corporation | Data interpolating circuit |
JPS6050667A (en) * | 1983-08-27 | 1985-03-20 | Sony Corp | Optical disc recording device |
US5163053A (en) * | 1988-10-24 | 1992-11-10 | Matsushita Electric Industrial Co., Ltd. | Audio signal demodulation circuit |
US5363384A (en) * | 1988-10-24 | 1994-11-08 | Matsushita Electric Industrial, Co., Ltd. | Audio signal demodulation circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0158578B2 (en) | 1989-12-12 |
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