JPS5795000A - Memory card testing circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of a test by controlling a check on read data by determining by the width of a selected block by a CS signal for selecting a memory module in a block. CONSTITUTION:In writing operation, a signal 40 is sent from an address, write data and control signal generating part 36 to a memory card 20 to be tested. At this time, the high-order part of an address signal enters an address high- order bit multiplexer 38, where it is decoded 37 to obtain CS signals 42-45 for respective blocks. In reading operation, signals are sent out of the circuits 36 and 37 in the same way with the writing operation, but neither write data nor a write control signal is sent by the signal 40. The read data 41 of a card 20 is passed through an OR circuit 31 and a read register circuit 32 and compared with comparison data 46 by a coincidence checking and detecting circuit 33; when both of them are coincident with each other, the data is passed and when not, it is regarded as an error, sending a coincidence output 47. Then, it is inputted to read data checking circuit 34 composed of an NAND gate to be NANDed with CS signals 42-45.